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11. 发明申请

WO2014042754A1 SELF-ALIGNED CARBON NANOSTRUCTURE FIELD EFFECT TRANSISTORS USING SELECTIVE DIELECTRIC DEPOSITION 审中-公开
标题翻译：使用选择性电介质沉积的自对准碳纳米管结构场效应晶体管
公开(公告)号：WO2014042754A1
公开(公告)日：2014-03-20
申请号：PCT/US2013/049215
申请日：2013-07-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , FARMER, Damon, B. , FRANKLIN, Aaron, D. , HAN, Shu-Jen , TULEVSKI, George, S.
发明人： FARMER, Damon, B. , FRANKLIN, Aaron, D. , HAN, Shu-Jen , TULEVSKI, George, S.
IPC分类号： H01L29/76
CPC分类号： H01L29/78669 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/775 , H01L29/78678 , H01L29/78696 , H01L51/0048 , H01L51/0516 , Y10S977/742
摘要： Self-aligned carbon nanostructure field effect transistor structures are provided, which are formed using selective dielectric deposition techniques. For example, a transistor device includes an insulating substrate and a gate electrode embedded in the insulating substrate. A dielectric deposition-prohibiting layer is formed on a surface of the insulating substrate surrounding the gate electrode. A gate dielectric is selectively formed on the gate electrode. A channel structure (such as a carbon nanostructure) is disposed on the gate dielectric A passivation layer is selectively formed on the gate dielectric. Source and drain contacts are formed on opposing sides of the passivation layer in contact with the channel structure. The dielectric deposition-prohibiting layer prevents deposition of dielectric material on a surface of the insulating layer surrounding the gate electrode when selectively forming the gate dielectric and passivation layer.
摘要翻译：提供了使用选择性电介质沉积技术形成的自对准碳纳米结构场效应晶体管结构。例如，晶体管器件包括绝缘衬底和嵌入绝缘衬底中的栅电极。在围绕栅电极的绝缘基板的表面上形成介电沉积禁止层。选择性地在栅电极上形成栅极电介质。沟道结构（例如碳纳米结构）设置在栅极电介质上钝化层选择性地形成在栅极电介质上。源极和漏极触点形成在与沟道结构接触的钝化层的相对侧上。当选择性地形成栅极电介质和钝化层时，介电沉积禁止层防止介电材料沉积在围绕栅电极的绝缘层的表面上。

12. 发明申请

WO2013012453A1 REPLACEMENT GATE ELECTRODE WITH PLANAR WORK FUNCTION MATERIAL LAYERS 审中-公开
标题翻译：具有平面工作功能材料层的更换门电极
公开(公告)号：WO2013012453A1
公开(公告)日：2013-01-24
申请号：PCT/US2012/027844
申请日：2012-03-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GUO, Dechao , HAN, Shu-Jen , WONG, Keith Kwong Hon , YUAN, Jun
发明人： GUO, Dechao , HAN, Shu-Jen , WONG, Keith Kwong Hon , YUAN, Jun
IPC分类号： H01L27/00
CPC分类号： H01L29/42364 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/165 , H01L29/41775 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L29/7848
摘要： In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function material portion to form a gate structure that enhances performance of a replacement gate field effect transistor.
摘要翻译：在替代栅极方案中，连续材料层沉积在栅极腔中的底表面和侧壁表面上。去除连续材料层的垂直部分以形成垂直部分不延伸到栅极腔的顶部的栅极部件。栅极元件可以用作栅极电介质或功函数材料部分，以形成增强替代栅极场效应晶体管性能的栅极结构。

13. 发明申请

WO2012177328A1 GRAPHENE OR CARBON NANOTUBE DEVICES WITH LOCALIZED BOTTOM GATES AND GATE DIELECTRIC 审中-公开
标题翻译：具有本地化底部门和门电介质的石墨或碳纳米管装置
公开(公告)号：WO2012177328A1
公开(公告)日：2012-12-27
申请号：PCT/US2012/036716
申请日：2012-05-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHEN, Zhihong , FRANKLIN, Aaron Daniel , HAN, Shu-Jen , HANNON, James Bowler , SAENGER, Katherine L. , TULEVSKI, George Stojan
发明人： CHEN, Zhihong , FRANKLIN, Aaron Daniel , HAN, Shu-Jen , HANNON, James Bowler , SAENGER, Katherine L. , TULEVSKI, George Stojan
IPC分类号： H03H11/46 , H01L29/16
CPC分类号： H01L29/7781 , B82Y10/00 , B82Y30/00 , H01L29/1075 , H01L29/1606 , H01L29/42384 , H01L29/4908 , H01L29/66742 , H01L29/78684 , H01L51/0023 , H01L51/0048 , H01L51/0545 , H01L51/055
摘要： Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.
摘要翻译：提供具有基于纳米材料的通道（例如，碳纳米管或石墨烯通道）的晶体管器件及其制造技术。一方面，提供一种晶体管器件。晶体管器件包括衬底; 衬底上的绝缘体; 嵌入绝缘体中的局部底栅，其中栅极的顶表面与绝缘体的表面基本共面; 底栅上的局部栅极电介质; 在所述局部栅极电介质的至少一部分上的碳基纳米结构材料，其中所述碳基纳米结构材料的一部分用作所述器件的通道; 并且导电源极和漏极接触到用作器件的源极和漏极区域的沟道的相对侧上的碳基纳米结构材料的一个或多个部分。

14. 发明申请

WO2013089944A2 FETS WITH HYBRID CHANNEL MATERIALS 审中-公开
标题翻译： FETS与混合通道材料
公开(公告)号：WO2013089944A2
公开(公告)日：2013-06-20
申请号：PCT/US2012/063831
申请日：2012-11-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GUO, Dechao , HAN, Shu-Jen , KIEWRA, Edward William , SHIU, Kuen-Ting
发明人： GUO, Dechao , HAN, Shu-Jen , KIEWRA, Edward William , SHIU, Kuen-Ting
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/8258 , H01L21/823807 , H01L27/0605
摘要： Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET.
摘要翻译：提供在同一CMOS电路内采用不同通道材料的技术。一方面，制造CMOS电路的方法包括以下步骤。提供了在绝缘体上具有第一半导体层的晶片。 STI用于将第一半导体层分成第一有源区和第二有源区。第一半导体层凹入第一有源区。第二半导体层在第一半导体层上外延生长，其中第二半导体层包括具有至少一个III族元素和至少一个V族元素的材料。使用第二半导体层作为n-FET的沟道材料，在第一有源区中形成n-FET。使用第一半导体层作为p-FET的沟道材料，在第二有源区中形成p-FET。

15. 发明申请

WO2005114243A3 MAGNETIC SENSOR ARRAY HAVING AN ANALOG FREQUENCY-DIVISION MULTIPLEXED OUTPUT 审中-公开
标题翻译：具有模拟频率多路复用输出的磁传感器阵列
公开(公告)号：WO2005114243A3
公开(公告)日：2006-12-07
申请号：PCT/US2005016799
申请日：2005-05-12
申请人： UNIV LELAND STANFORD JUNIOR , WANG SHAN X , HAN SHU JEN
发明人： WANG SHAN X , HAN SHU JEN
IPC分类号： G01R33/00 , G01N33/543 , G01R33/09 , G01R33/12
CPC分类号： G01R33/09 , B82Y25/00 , G01N33/5438 , G01R33/093 , G01R33/12 , G01R33/1269 , Y10T436/13
摘要： A magnetic sensor array including magnetoresistive sensor elements having outputs combined by frequency division multiplexing (FDM) is provided. Each sensor element provides an input to a mixer which provides a distinct frequency shift. Preferably, time division multiplexing is also used to combine sensor element outputs. Each sensor element is typically in proximity to a corresponding sample. The sensor elements are preferably subarrays having row and column addressable sensor element pixels. This arrangement provides multiple sensor pixels for each sample under test. Multiplexing of sensor element outputs advantageously reduces readout time. A modulated external magnetic field is preferably applied during operation, to reduce the effect of 1/f noise on the sensor element signals. The effect of electromagnetic interference (EMI) induced by the magnetic field on sensor element signals is advantageously reduced by the mixing required for FDM.
摘要翻译：提供了包括具有通过频分复用（FDM）组合的输出的磁阻传感器元件的磁传感器阵列。每个传感器元件提供输入到提供不同频率偏移的混频器。优选地，时分复用也用于组合传感器元件输出。每个传感器元件通常接近相应的样品。传感器元件优选地具有行和列可寻址传感器元件像素的子阵列。这种布置为每个被测样品提供了多个传感器像素。传感器元件输出的多路复用有利于减少读出时间。优选在操作期间施加调制的外部磁场，以减少1 / f噪声对传感器元件信号的影响。通过FDM所需的混合有利地减小了由磁场引起的电磁干扰（EMI）对传感器元件信号的影响。

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