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121. 发明申请

WO00029937A2 COMPUTER SYSTEM, COMPUTER-READABLE STORAGE MEDIUM AND METHOD OF OPERATING SAME, AND METHOD OF OPERATING THAT SYSTEM 审中-公开
标题翻译：计算机系统，计算机可读存储介质及其操作方法以及操作系统的方法
公开(公告)号：WO00029937A2
公开(公告)日：2000-05-25
申请号：PCT/GB1999/000788
申请日：1999-03-16
IPC分类号： G06F11/28 , G06F9/40 , G06F9/42 , G06F9/44 , G06F9/45 , G06F9/455 , G06F9/46 , G06F9/48 , G06F11/36 , G06F12/02 , G06F9/00
CPC分类号： G06F9/4812 , G06F8/4442 , G06F8/445 , G06F9/4484 , G06F9/449 , G06F9/4491 , G06F9/455 , G06F9/45516 , G06F11/3612 , G06F12/0269 , G06F2209/481 , Y10S707/99932 , Y10S707/99953 , Y10S707/99956
摘要： A computer system described may have features relating to one or more of dynamic compilation of a dominant path, including using pre-exception condition checks, outliers and/or class loaders, to dispatch mechanisms for interface methods, to management and deletion of code buffers, to test and verification of compiled code, to return barriers in garbage collection, grey packet management in garbage collection, to device driver interrupt handlers, and/or to data structures comprising a list. The invention finds particular application for systems including a virtual machine 2000. The virtual machine 2000 is installed in an item of equipement 2002 and is coupled to one or more applications 2004 and to items of hardware 2006 of the equipement 2002. Advantages include increased speed of execution and reduced memory footprint.
摘要翻译：所描述的计算机系统可以具有与主要路径的动态编译中的一个或多个相关的特征，包括使用异常情况检查，异常值和/或类加载器，调度接口方法的机制，代码缓冲器的管理和删除，测试和验证编译代码，将垃圾收集中的障碍，垃圾回收中的灰色数据包管理，设备驱动程序中断处理程序和/或包含列表的数据结构。本发明发现对包括虚拟机2000的系统的特定应用。虚拟机2000安装在设备2002中，并且耦合到设备2002的一个或多个应用2004和硬件2006的各项。优点包括提高速度执行和减少内存占用。

122. 发明申请

WO0016191A3 ACCURATE METHOD FOR INLINING VIRTUAL CALLS 审中-公开
标题翻译：用于插入虚拟电话的精确方法
公开(公告)号：WO0016191A3
公开(公告)日：2000-05-25
申请号：PCT/US9920576
申请日：1999-09-08
申请人： SUN MICROSYSTEMS INC
发明人： DETLEFS DAVID L , AGESEN OLE
IPC分类号： G06F9/42 , G06F9/45 , G06F9/44
CPC分类号： G06F9/4431
摘要： A computer system (10) is configured as a compiler to translate source code (Fig. 4) into object code (Fig. 6). The source code calls a polymorphic method on a receiver object. The compiler inlines the polymorphic method and guards the inlining with guard code that causes the executing microprocessor to skip the inlining in favor of a virtual method call when it determines that the inlined code is not appropriate for the receiver object. To make that determination, the guard code compares the address of the method version that has been inlined with the receiver object's pointer to its version of the polymorphic method.
摘要翻译：计算机系统（10）被配置为将源代码（图4）转换成目标代码（图6）的编译器。源代码调用接收器对象上的多态方法。编译器对多态方法进行了内联操作，并通过保护代码来防止内联，这会导致正在执行的微处理器在确定内联代码不适合接收方对象时跳过内联以支持虚拟方法调用。为了做出这个决定，守护代码将已经内联的方法版本的地址与接收者对象的指针的地址进行比较，以将其与多态方法的版本进行比较。

123. 发明申请

WO99063433A1 REFERENCING A METHOD IN OBJECT-BASED PROGRAMMING 审中-公开
标题翻译：参考基于对象编程的方法
公开(公告)号：WO99063433A1
公开(公告)日：1999-12-09
申请号：PCT/US1999/012299
申请日：1999-06-03
IPC分类号： G06F9/44 , G06F9/42
CPC分类号： G06F9/449
摘要： Method and apparatus for encapsulating a reference to a method in object-based programming systems and ensuring that the reference is safe are disclosed. The method of encapsulation provides for: a) defining an entity that defines the shape of the method to be referenced; b) obtaining a reference to a method; c) storing this reference in arbitrary data structures; d) passing the reference to code written by other parties; e) enabling invocation of the method by anyone holding the method reference; and f) enabling the holder of a method reference to determine the target object and method being referenced. These objectives are achieved in a strongly typed manner, making it possible for: a) developers to learn of type mismatch problems early (at compile-time) rather than late (at run-time); and b) development tools to present information to developers about the shape of components that use delegates. In addition, a model of event based programming is disclosed, wherein event-related code can be encapsulated in delegates.
摘要翻译：公开了一种用于封装对基于对象的编程系统中的方法的参考并确保参考是安全的方法和装置。封装方法提供：a）定义定义要引用的方法的形状的实体; b）获得对方法的引用; c）将此参考存储在任意数据结构中; d）通过对其他方面编写的代码的引用; e）允许任何持有方法引用的方法的调用; 以及f）使方法引用的持有者能够确定所参考的目标对象和方法。这些目标是以强力类型的方式实现的，从而有可能：a）开发人员早期（在编译时）而不是迟到（在运行时）学习类型不匹配问题; 和b）开发工具向开发人员介绍使用代表的组件的形状。另外，公开了一种基于事件的编程的模型，其中事件相关代码可以被封装在委托中。

124. 发明申请

WO99056209A1 APPARATUS WITH CONTEXT SWITCHING CAPABILITY 审中-公开
标题翻译：具有上下文切换能力的装置
公开(公告)号：WO99056209A1
公开(公告)日：1999-11-04
申请号：PCT/US1999/004134
申请日：1999-02-25
IPC分类号： G06F9/42 , G06F9/30 , G06F9/46 , G06F9/48 , G11C7/00
CPC分类号： G06F9/30141 , G06F9/30116 , G06F9/30123 , G06F9/462 , G11C7/00
摘要： The present invention relates to a data processing unit, comprising at least one register having at least one read port and one write port. The register has at least two memory cells each having a write line and a read line, first switching means having inputs and one output for coupling said read line of one of said memory cells with said read port, second switching means for coupling said write line of one of said memory cells with said write port.
摘要翻译：本发明涉及一种数据处理单元，包括至少一个具有至少一个读端口和一个写端口的寄存器。寄存器具有至少两个具有写入线和读取线的存储单元，第一开关装置具有用于将所述存储单元之一的所述读取线与所述读取端口耦合的输入和一个输出;第二开关装置，用于将所述写入线的所述存储单元之一与所述写入端口。

125. 发明申请

WO98057255A1 METHOD FOR MODIFYING CODE SEQUENCES AND RELATED DEVICE 审中-公开
标题翻译：修改代码序列和相关设备的方法
公开(公告)号：WO98057255A1
公开(公告)日：1998-12-17
申请号：PCT/FR1998/001228
申请日：1998-06-12
IPC分类号： G06F9/42 , G06F9/26 , G06F9/32 , G06F9/445 , G06F11/00 , G06F11/20
CPC分类号： G06F9/328 , G06F8/66 , G06F9/268
摘要： The invention concerns a device for modifying code sequences written in a medium memory (2) comprising a central unit (1), said memory containing a main programme executable by the central unit (1) which also comprises a second non-volatile programmable memory (3), and a third working memory.(4). The invention is characterised in that a rerouting table TAB_DER contained in the second programmable memory contains at least one field containing a new code sequence reference data, rerouting means for delayed rerouting of the executed code sequence towards the new code sequence written in one of the three memories and means in the new code sequence for returning to a point of the sequence before rerouting.
摘要翻译：本发明涉及一种用于修改写入包括中央单元（1）的介质存储器（2）中的代码序列的设备，所述存储器包含可由中央单元（1）执行的主程序，该主程序还包括第二非易失性可编程存储器 3）和第三工作存储器（4）。本发明的特征在于，包含在第二可编程存储器中的重新路由表TAB_DER包含至少一个包含新的代码序列参考数据的字段，用于将执行的代码序列延迟重新路由到以三个新代码序列中的记忆和手段，用于在重新路由之前返回到序列的一个点。

126. 发明申请

WO2017001905A1 METHOD AND SYSTEM FOR DYNAMIC INDEXATION AND LOADING OF MODULE CODES 审中-公开
标题翻译：动态指标和模块代码加载的方法和系统
公开(公告)号：WO2017001905A1
公开(公告)日：2017-01-05
申请号：PCT/IB2015/058961
申请日：2015-11-19
申请人： YANDEX EUROPE AG , YANDEX LLC , YANDEX INC.
发明人： ZINCHUK, Aleksandr Aleksandrovich , KONSTANTINOV, Sergey Sergeevich
IPC分类号： G06F9/42
CPC分类号： G06F9/44521 , G06F8/61 , G06F17/2247 , G06F17/30902 , H04L67/10 , H04L67/34
摘要： Computing device and a method for loading module codes, the module codes required for executing an action, the method comprising: receiving, by the computing device, a request for executing the action, the action being executable using a first module code; acquiring, from the first predetermined index a first module code reference indicating a first module code location and the indication that executing the first module code requires a second module code; acquiring, from a second predetermined index, a second module code reference, the second module code reference indicating a second module code location; based on the first module code reference, acquiring the first module code from the first module code location; based on the second module code reference, acquiring the second module code from the second module code location; executing the action by running the first module code and the second module code.
摘要翻译：计算设备和用于加载模块代码的方法，用于执行动作所需的模块代码，所述方法包括：由所述计算设备接收执行所述动作的请求，所述动作可使用第一模块代码执行; 从所述第一预定索引获取指示第一模块代码位置的第一模块代码参考和执行所述第一模块代码的指示需要第二模块代码; 从第二预定索引获取第二模块代码参考，所述第二模块代码参考指示第二模块代码位置; 基于所述第一模块代码参考，从所述第一模块代码位置获取所述第一模块代码; 基于所述第二模块代码参考，从所述第二模块代码位置获取所述第二模块代码; 通过运行第一个模块代码和第二个模块代码来执行该操作。

127. 发明申请

WO2015113070A1 PROCESSOR LOOP BUFFER 审中-公开
标题翻译：处理器环路缓冲区
公开(公告)号：WO2015113070A1
公开(公告)日：2015-07-30
申请号：PCT/US2015/013149
申请日：2015-01-27
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS DEUTSCHLAND GMBH , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： WIENCKE, Christian , LEDWA, Ralph , REICHEL, Norbert
IPC分类号： G06F9/30 , G06F9/42
CPC分类号： G06F9/325 , G06F9/3013 , G06F9/381 , G06F9/3814
摘要： In described examples, a processor (100) includes an execution unit (108) and an instruction fetch buffer (104). The execution unit (108) is configured to execute instructions. The instruction fetch buffer (104) is configured to store instructions for execution by the execution unit (108). The instruction fetch buffer (104) includes a loop buffer configured to store instructions of an instruction loop for repeated execution by the execution unit (108). The loop buffer includes buffer control logic. The buffer control logic includes pointers, and is configured to predecode a loop jump instruction, identify loop start and loop end instructions using the predecoded loop jump instruction and pointers, and control non-sequential instruction execution of the instruction loop. The width of the pointers is determined by loop buffer length and is less than a width of an address bus for fetching the instructions stored in the loop buffer from an instruction memory.
摘要翻译：在所描述的示例中，处理器（100）包括执行单元（108）和指令获取缓冲器（104）。执行单元（108）被配置为执行指令。指令获取缓冲器（104）被配置为存储由执行单元（108）执行的指令。指令获取缓冲器（104）包括循环缓冲器，该循环缓冲器被配置为存储由执行单元（108）重复执行的指令循环的指令。循环缓冲器包括缓冲器控制逻辑。缓冲器控制逻辑包括指针，并且被配置为使用预解码循环跳转指令和指针来预循环跳转指令，识别循环开始和循环结束指令，并且控制指令循环的非顺序指令执行。指针的宽度由循环缓冲区长度确定，并且小于用于从指令存储器读取存储在循环缓冲器中的指令的地址总线的宽度。

128. 发明申请

WO2010014286A1 BRANCH TARGET BUFFER ALLOCATION 审中-公开
标题翻译：分支目标缓冲区分配
公开(公告)号：WO2010014286A1
公开(公告)日：2010-02-04
申请号：PCT/US2009/043452
申请日：2009-05-11
申请人： FREESCALE SEMICONDUCTOR INC. , MOYER, William, C. , SCOTT, Jeffrey, W.
发明人： MOYER, William, C. , SCOTT, Jeffrey, W.
IPC分类号： G06F9/32 , G06F9/38 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/3844
摘要： A data processing system (10) and method are provided for allocating an entry in a branch target buffer (BTB) (14). The method comprises: receiving a branch instruction to be executed in a data processor(40); determining that the BTB does not include an entry corresponding to the branch instruction; identifying an entry in the BTB for allocation, the identified entry in the BTB comprising a target identifier (30) and a first prediction value (32) for a previously received branch instruction; determining whether to allocate the branch instruction to the identified entry in the BTB based on a comparison of the first prediction value to a second prediction value, wherein the second prediction value is generated from a branch history table (BHT) (20); and allocating the branch instruction to the identified entry if the second prediction value indicates a more strongly taken prediction than the first prediction value.
摘要翻译：提供了一种用于在分支目标缓冲器（BTB）中分配条目的数据处理系统（10）和方法（14）。该方法包括：接收要在数据处理器（40）中执行的分支指令; 确定BTB不包括对应于分支指令的条目; 识别BTB中用于分配的条目，BTB中的识别条目包括用于先前接收的分支指令的目标标识符（30）和第一预测值（32）; 基于所述第一预测值与第二预测值的比较，确定是否将所述分支指令分配给所述BTB中的所述识别的条目，其中，所述第二预测值是从分支历史表（BHT）（20）生成的。以及如果所述第二预测值指示比所述第一预测值更强烈地采取预测，则将所述分支指令分配给所识别的条目。

129. 发明申请

WO2008026957A1 A SPLIT STAGE CALL SEQUENCE RESTORATION METHOD 审中-公开
标题翻译：分阶段呼叫序列恢复方法
公开(公告)号：WO2008026957A1
公开(公告)日：2008-03-06
申请号：PCT/RU2006/000463
申请日：2006-08-30
申请人： INTEL CORPORATION , BRATANOV, Stanislav Viktorovich , ALEXANDROV, Alexei Gennadyevich
发明人： BRATANOV, Stanislav Viktorovich , ALEXANDROV, Alexei Gennadyevich
IPC分类号： G06F9/42 , G06F11/34
CPC分类号： G06F11/3471 , G06F9/44521 , G06F9/4486 , G06F2212/451
摘要： Embodiments of the present invention provide for collecting a minimal subset of task execution context in real time and for restoring the task execution context and performing procedure frame unwinding operations at a post-processing stage. A first data structure may be constructed in real time to contain procedure linkage information along with references to the memory area or to a processor register context where each procedure linkage information element (procedure return address or a procedure frame pointer) was originally found. Procedure return addresses may be determined by decoding the instruction preceding the address in question and checking if it is a procedure call instruction. Procedure return addresses may also be determined using other methods (e.g., by checking whether the memory region the address in question belongs to is executable) if the probability of retrieving the correct result is acceptable for a particular area of application of an embodiment of the present invention. Procedure frame pointers may be determined as the conventional memory area elements whose value points back to the conventional memory area. Procedure frame pointers, depending on particular processor architecture, may also have other properties that differentiate them from other elements of the conventional memory area. The conventional memory area for purposes of the present invention may be non-contiguous. The contents of first data structure may then be employed in reconstruction of the task execution environment at the post-processing stage. Then, the procedure frame unwinding operations may be performed over the restored task execution context.
摘要翻译：本发明的实施例提供了实时收集任务执行上下文的最小子集，并且用于在后处理阶段恢复任务执行上下文和执行过程帧展开操作。可以实时地构建第一数据结构以包含过程链接信息以及对存储区域的引用，或包含最初找到每个过程链接信息元素（过程返回地址或过程帧指针）的处理器寄存器上下文。过程返回地址可以通过对所述地址之前的指令进行解码并检查其是否是过程调用指令来确定。过程返回地址也可以使用其他方法来确定（例如，通过检查所讨论的地址是否可执行的内存区域），如果检索正确结果的概率对于本发明实施例的特定应用领域是可以接受的发明。过程帧指针可以被确定为其值指向常规存储区域的常规存储器区域元素。取决于特定处理器架构的过程帧指针也可以具有将它们与常规存储器区域的其他元件区分开的其他属性。用于本发明目的的常规存储区可以是不连续的。然后可以在后处理阶段将第一数据结构的内容用于任务执行环境的重建。然后，可以在恢复的任务执行上下文中执行过程帧展开操作。

130. 发明申请

WO2007148132A1 METHOD AND APPARATUS FOR HANDLING EXCEPTIONS DURING BINDING TO NATIVE CODE 审中-公开
标题翻译：在绑定到本规范期间处理例外的方法和装置
公开(公告)号：WO2007148132A1
公开(公告)日：2007-12-27
申请号：PCT/GB2007/050343
申请日：2007-06-19
申请人： TRANSITIVE LIMITED , BARRACLOUGH, Gavin , WAN, Kit, Man , HUMMAIDA, Abdul, Rahman
发明人： BARRACLOUGH, Gavin , WAN, Kit, Man , HUMMAIDA, Abdul, Rahman
IPC分类号： G06F9/45 , G06F9/42
CPC分类号： G06F9/45516 , G06F2209/481
摘要： A target computing system (10) is arranged to perform program code conversion from subject code (17) executable by a subject computing architecture (1) into target code (21) executable by the target computing system (10), and then execute the target code (21). In one embodiment, the target computing system (10) performs dynamic binary translation. Also, the target computing system (10) handles exceptions during binding to native code. Here, native code binding executes a portion of native code (28) (e.g. a native library function) in place of translating a portion of the subject code (17) (e.g. a subject library function) into the target code (21). When an exception occurs during execution of the portion of native code (28), the target computing system (10) saves a target state (T') which represents a current point of execution for the portion of native code (28), and creates a subject state (S') which represents an emulated point of execution in the subject computing architecture (1). The exception is handled through a subject exception handler unit (170, 170') with reference to the subject state (S'), such that, upon resuming execution from the exception using the provided subject state (S'), the saved target state (T') is restored to resume execution in the section of portion of native code (28). In one embodiment, the subject state (S') links to the saved target state (T') through a recovery unit (192).
摘要翻译：目标计算系统（10）被布置为执行由主体计算架构（1）可执行的主题代码（17）的程序代码转换为可由目标计算系统（10）执行的目标代码（21），然后执行目标代码（21）。在一个实施例中，目标计算系统（10）执行动态二进制转换。此外，目标计算系统（10）在绑定到本机代码期间处理异常。这里，本地代码绑定执行本地代码（28）的一部分（例如本地库函数），代替将主题代码（17）的一部分（例如，主题库函数）转换为目标代码（21）。当执行本机代码部分（28）期间出现异常时，目标计算系统（10）保存表示本地代码（28）部分的当前执行点的目标状态（T'），并创建主题状态（S'），其表示主体计算架构（1）中的仿真执行点。通过参照对象状态（S'）的主题异常处理单元（170,170'）来处理异常，使得当使用所提供的主体状态（S'）从异常恢复执行时，保存的目标状态（T'）被恢复以在本地代码（28）的部分的部分中恢复执行。在一个实施例中，主体状态（S'）通过恢复单元（192）链接到保存的目标状态（T'）。

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