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91. 发明申请

WO2013124713A1 CLOCK DISTRIBUTION MODULE, SYNCHRONOUS DIGITAL SYSTEM AND METHOD THEREFOR 审中-公开
标题翻译：时钟分配模块，同步数字系统及其方法
公开(公告)号：WO2013124713A1
公开(公告)日：2013-08-29
申请号：PCT/IB2012/050867
申请日：2012-02-24
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , DZEBISASHVILI, David , FLESHEL, Leonid
发明人： PRIEL, Michael , DZEBISASHVILI, David , FLESHEL, Leonid
IPC分类号： H03K5/15 , G06F1/04
CPC分类号： H04L25/45 , G06F1/10 , H04L25/44
摘要： A clock distribution module for a digital synchronous system is described. The clock distribution module comprising a first node arranged to comprise a clock signal comprising a propagation delay relative to a reference clock signal, at least one further node arranged to comprise a clock signal comprising a propagation delay relative to the reference clock signal corresponding to that of the first node, and a clock configuration module. The clock configuration module is arranged to receive at least one indication of clock skew between the first node and at least one further node of the clock distribution module, and to selectively couple the first node to the at least one further node based at least partly on the at least one indication of clock skew there between.
摘要翻译：描述了用于数字同步系统的时钟分配模块。所述时钟分配模块包括被布置为包括相对于参考时钟信号的传播延迟的时钟信号的第一节点，至少一个另外的节点，被布置为包括时钟信号，该时钟信号包括相对于参考时钟信号的参考时钟信号的传播延迟第一个节点和一个时钟配置模块。时钟配置模块被布置成接收时钟分配模块的第一节点和至少一个另外节点之间的时钟偏移的至少一个指示，并且至少部分地基于第一节点选择性地将第一节点耦合到至少一个另外的节点其间的时钟偏移的至少一个指示。

92. 发明申请

WO2010029389A1 METHOD AND APPARATUS FOR GATING A CLOCK SIGNAL 审中-公开
标题翻译：评估时钟信号的方法和装置
公开(公告)号：WO2010029389A1
公开(公告)日：2010-03-18
申请号：PCT/IB2008/053725
申请日：2008-09-15
申请人： FREESCALE SEMICONDUCTOR, INC. , SOFER, Sergey , DABUSH, Ami , PRIEL, Michael
发明人： SOFER, Sergey , DABUSH, Ami , PRIEL, Michael
IPC分类号： H03K19/096 , G06F1/08 , H03L7/081 , H04L7/033
CPC分类号： H03K19/096 , G06F1/08 , H03K19/0016
摘要： A semiconductor device (400) comprising clock gating logic (405). The clock gating logic (405) comprises clock freezing logic (410) arranged to receive a selected clock signal (415) and an enable signal (460). The clock freezing logic (410) is further arranged to output a gated clock signal (420) substantially corresponding to the selected clock signal (415) when the enable signal (460) comprises an inactive state, and to freeze the output gated clock signal (420) when the enable signal (460) comprises an active state. The clock gating logic (405) further comprises polarity comparison logic (425) arranged to compare polarities of an input clock signal (430) and the gated clock signal (420), and selector logic (435) arranged to select from the input clock signal (430) and an inverted input clock signal (445), based on a result (440) of a comparison of the polarities of the input clock signal (430) and the gated clock signal (420), and to provide the selected clock signal (415) to the clock freezing logic (410). The polarity comparison logic (425) and the selector logic (435) being further arranged such that, upon the enable signal (460) transitioning from an active state to an inactive state, the selected clock signal (415) provided to the clock freezing logic (410) comprises a polarity substantially equivalent to that of the gated clock signal (420).
摘要翻译：一种包括时钟选通逻辑（405）的半导体器件（400）。时钟门控逻辑（405）包括布置成接收所选择的时钟信号（415）和使能信号（460）的时钟冻结逻辑（410）。时钟冻结逻辑（410）还被布置成当使能信号（460）包括非活动状态时，输出基本对应于所选时钟信号（415）的门控时钟信号（420），并且将输出门控时钟信号 420）当使能信号（460）包括有效状态时。时钟门控逻辑（405）还包括被布置为比较输入时钟信号（430）和选通时钟信号（420）的极性的极性比较逻辑（425），以及布置成从输入时钟信号（430）和门控时钟信号（420）的极性的比较的结果（440），并且提供所选择的时钟信号（430）和反相输入时钟信号（445）（415）连接到时钟冻结逻辑（410）。极性比较逻辑（425）和选择器逻辑（435）进一步布置成使得在使能信号（460）从激活状态转换到非活动状态时，所选择的时钟信号（415）提供给时钟冻结逻辑（410）包括与门控时钟信号（420）的极性相当的极性。

93. 发明申请

WO2008139275A1 SYSTEM AND METHOD FOR SECURE REAL TIME CLOCKS 审中-公开
标题翻译：用于保证实时时钟的系统和方法
公开(公告)号：WO2008139275A1
公开(公告)日：2008-11-20
申请号：PCT/IB2007/052713
申请日：2007-05-11
申请人： FREESCALE SEMICONDUCTOR, INC. , VOORWINDEN, Cor , PRIEL, Michael
发明人： VOORWINDEN, Cor , PRIEL, Michael
IPC分类号： G04G3/02 , G06F1/14 , G06F1/32
CPC分类号： G04G3/02 , G06F1/14 , G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A secure real time clock (RTC) system (1 ) is provided, comprising a secure RTC (3), a frequency signal generator (5, 7), and a frequency adjuster (9, 11 ) connected between the secure RTC (3) and the frequency signal generator (5,7) to receive a signal having a first frequency from the frequency signal generator (5, 7). On receipt of a first control signal the frequency adjuster outputs the signal having the first frequency to the secure RTC (3), and on receipt of a second control signal the frequency adjuster adjusts the signal having the first frequency to generate a signal having a second frequency, the second frequency being lower than the first frequency, and outputs the signal having the second frequency to the secure RTC (3). A clock line (23) transmits the signal having the first frequency and the signal having the second frequency from the frequency adjuster (9, 11 ) to the secure RTC (3), and has a first power consumption when transmitting the signal having the first frequency and a second power consumption when transmitting the signal having the second frequency, the first power consumption being greater than the second power consumption.
摘要翻译：提供安全的实时时钟（RTC）系统（1），其包括安全RTC（3），频率信号发生器（5,7）和频率调节器（9,11），连接在安全RTC（3）和频率信号发生器（5,7），以从频率信号发生器（5,7）接收具有第一频率的信号。在接收到第一控制信号时，频率调节器将具有第一频率的信号输出到安全RTC（3），并且在接收到第二控制信号时，频率调节器调节具有第一频率的信号以产生具有第二频率的信号频率，第二频率低于第一频率，并将具有第二频率的信号输出到安全RTC（3）。时钟线（23）将具有第一频率的信号和具有第二频率的信号从频率调节器（9,11）发送到安全RTC（3），并且当发送具有第一频率的信号时，具有第一功率消耗频率和第二功率消耗，当发送具有第二频率的信号时，第一功率消耗大于第二功率消耗。

94. 发明申请

WO2006131143A1 DEVICE AND METHOD FOR MEDIA ACCESS CONTROL 审中-公开
标题翻译：用于媒体访问控制的设备和方法
公开(公告)号：WO2006131143A1
公开(公告)日：2006-12-14
申请号：PCT/EP2005/007886
申请日：2005-06-10
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , CHUN, Christopher , CHUN, Christopher , LEE, Gordon, P. , VOORWINDEN, Cor
发明人： PRIEL, Michael , CHUN, Christopher , CHUN, Christopher , LEE, Gordon, P. , VOORWINDEN, Cor
IPC分类号： G06F13/40 , G06F13/376 , G06F1/08 , G06F1/32
CPC分类号： G06F13/376 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F1/3296 , Y02D10/126 , Y02D10/151 , Y02D10/172
摘要： A method (100) for media access control, the method includes generating (180) at least one media access grant in response to at least one media access request. The method is characterized by monitoring (130) a data line, while maintaining at least a clock line in a low power mode, to detect at least one media access request generated by at least one component connected to the data line and to the clock line; and forcing (140) the at least clock line to exit the low power mode and starting a contention prevention period, when the media access controller or at least one component requests to access the data line. A device (400) including multiple components (420) that are connected to a data line (430), and adapted to transmit information over the data line at a transmission rate responsive to a first clock rate. The device (400) is characterized by further including a clock signal provider (415) that is adapted to provide a high frequency clock signal over the data line and further adapted to determine, before a completion of the transmitting and in response to the transmitted information, when to substantially reduce the clock rate.
摘要翻译：一种用于媒体访问控制的方法（100），所述方法包括响应于至少一个媒体访问请求生成（180）至少一个媒体访问许可。该方法的特征在于，在保持低功率模式下的至少一个时钟线的同时监视（130）数据线，以检测由连接到数据线和时钟线的至少一个组件产生的至少一个媒体访问请求 ; 以及当所述媒体访问控制器或至少一个组件请求访问所述数据线时，迫使（140）所述至少时钟线退出所述低功率模式并开始争用预防时段。一种包括连接到数据线（430）的多个组件（420）并且适于以响应于第一时钟速率的传输速率通过数据线传输信息的设备（400）。该装置（400）的特征在于还包括时钟信号提供器（415），其适于在数据线上提供高频时钟信号，并且还适于在完成发送之前确定并且响应所发送的信息，何时大幅度降低时钟频率。

95. 发明申请

WO2006131142A1 METHOD AND DEVICE FOR FRAME SYNCHRONIZATION 审中-公开
标题翻译：用于帧同步的方法和装置
公开(公告)号：WO2006131142A1
公开(公告)日：2006-12-14
申请号：PCT/EP2005/007885
申请日：2005-06-10
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , CHUN, Christopher , LEE, Gordon, P. , VOORWINDEN, Cor
发明人： PRIEL, Michael , CHUN, Christopher , LEE, Gordon, P. , VOORWINDEN, Cor
IPC分类号： G06F13/42
CPC分类号： G06F13/4291 , Y02D10/14 , Y02D10/151
摘要： A method (10) for frame synchronization, the method (10) includes providing (30) a high frequency clock signal over a clock line during a transmission of information over a data line connected to a media access controller (410) and to at least one component (421); characterized by defining (20) a short synchronization period; processing (40) at least one signal conveyed over the data line during the short synchronization period to determine a presence of a synchronization error; and maintaining (70) at least the clock line in a low power mode when the data line is substantially idle. A device (400) having frame synchronization capabilities, the device includes a clock signal provider (415) and at least one component (421) connected to a data line (430). The clock signal provider (415) is adapted to provide a high frequency clock signal over a clock line during a transmission of information over the data line. The at least one component (421) is adapted to process at least one signal conveyed over the data line during a short synchronization period to determine a presence of a synchronization error. The device (400) is further adapted to maintain at least the clock line in a low power mode when the data line is substantially idle.
摘要翻译：一种用于帧同步的方法（10），所述方法（10）包括在通过连接到媒体访问控制器（410）的数据线上的信息传输期间在时钟线上提供（30）高频时钟信号，并且至少一个组件（421）; 其特征在于定义（20）短同步时段; 处理（40）在短同步周期期间通过数据线传送的至少一个信号以确定同步误差的存在; 并且当数据线基本上空闲时，至少将时钟线保持（70）为低功率模式。一种具有帧同步能力的设备（400），该设备包括连接到数据线（430）的时钟信号提供器（415）和至少一个组件（421）。时钟信号提供器（415）适于在数据线上的信息传输期间通过时钟线提供高频时钟信号。所述至少一个组件（421）适于处理在短同步周期期间通过所述数据线路传送的至少一个信号，以确定存在同步错误。所述设备（400）还适用于当所述数据线基本为空闲时，至少将所述时钟线保持在低功率模式。

96. 发明申请

WO2014108737A1 METHOD AND APPARATUS FOR PERFORMING LOGIC SYNTHESIS 审中-公开
标题翻译：用于执行逻辑合成的方法和装置
公开(公告)号：WO2014108737A1
公开(公告)日：2014-07-17
申请号：PCT/IB2013/050153
申请日：2013-01-08
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , BABITSKY, Eliya , BERKOVITZ, Asher , NUSIMOVICH, Vladimir
发明人： PRIEL, Michael , BABITSKY, Eliya , BERKOVITZ, Asher , NUSIMOVICH, Vladimir
IPC分类号： G06F17/50 , G06F1/00
CPC分类号： G06F17/505 , G06F17/5045
摘要： A method of performing logic synthesis of at least a part of an integrated circuit (IC) design. The method comprises identifying a first and at least one further module within the IC design that are mutually exclusive, selecting at least one register element within the first identified module and at least one register element within the at least one further identified module to be shared, and merging the first and at least one further mutually exclusive modules such that at least one common register element is shared between the first and at least one further mutually exclusive modules for the register elements selected to be shared.
摘要翻译：执行集成电路（IC）设计的至少一部分的逻辑合成的方法。该方法包括识别IC设计中的第一和至少一个彼此排斥的另外的模块，选择第一识别的模块内的至少一个寄存器元件和至少一个另外识别的模块中的至少一个寄存器元件以进行共享，并且合并第一和至少一个另外的互斥模块，使得至少一个公共寄存器元件在被选择被共享的寄存器元件的第一和至少一个另外的互斥模块之间被共享。

97. 发明申请

WO2014108735A1 METHOD AND APPARATUS FOR CALCULATING DELAY TIMING VALUES FOR AN INTEGRATED CIRCUIT DESIGN 审中-公开
标题翻译：用于计算集成电路设计的延迟时序值的方法和装置
公开(公告)号：WO2014108735A1
公开(公告)日：2014-07-17
申请号：PCT/IB2013/050151
申请日：2013-01-08
申请人： FREESCALE SEMICONDUCTOR, INC. , BERKOVITZ, Asher , PRIEL, Michael , SOFER, Sergey
发明人： BERKOVITZ, Asher , PRIEL, Michael , SOFER, Sergey
IPC分类号： G06F17/50 , G01R31/28 , H03K5/13
CPC分类号： G06F17/5031 , G06F17/5059 , G06F17/5081 , G06F2217/84 , H03K3/0375
摘要： A method of calculating at least one delay timing value for at least one setup timing stage within an integrated circuit design. The method comprises applying Negative/Positive Bias Temperature Instability, N/PBTI, compensation margins to delay values for elements within the at least one setup timing stage, and calculating the at least one delay timing value for the at least one setup timing stage based at least partly on the N/PBTI compensated delay values. The method further comprises identifying at least partially equivalent elements within parallel timing paths of the at least one setup timing stage, and applying reduced N/PBTI compensation margins to delay values for the identified at least partially equivalent elements within parallel timing paths of the at least one setup timing stage.
摘要翻译：一种为集成电路设计中的至少一个建立定时级计算至少一个延迟定时值的方法。该方法包括应用负/正偏压温度不稳定性，N / PBTI，补偿余量以延迟至少一个建立定时级内的元件的值，以及基于以下步骤计算至少一个建立时序阶段的至少一个延迟定时值：至少部分地基于N / PBTI补偿延迟值。所述方法还包括在所述至少一个建立定时阶段的并行定时路径内识别至少部分等效的元素，以及施加减少的N / PBTI补偿余量以在所述至少一个建立定时阶段的并行定时路径内对所识别的至少部分等效的元素的值进行延迟一个设置定时阶段。

98. 发明申请

WO2014068368A1 METHOD AND APPARATUS FOR AT-SPEED SCAN SHIFT FREQUENCY TEST OPTIMIZATION 审中-公开
标题翻译：用于高速扫描频率测试优化的方法和装置
公开(公告)号：WO2014068368A1
公开(公告)日：2014-05-08
申请号：PCT/IB2012/056019
申请日：2012-10-30
申请人： FREESCALE SEMICONDUCTOR, INC. , SOFER, Sergey , BERKOVITZ, Asher , PRIEL, Michael
发明人： SOFER, Sergey , BERKOVITZ, Asher , PRIEL, Michael
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318536 , G01R31/318575 , G01R31/318577 , G01R31/318594
摘要： There is provided an integrated circuit comprising at least one logic path, comprising a plurality of sequential logic elements operably coupled into a scan chain to form at least one scan chain under test, at least one IR drop sensor operably coupled to the integrated circuit power supply, operable to output a first logic state when a sensed supply voltage is below a first predefined value and to output a second logic state when the sensed supply voltage is above the first predefined value, at least one memory buffer operably coupled to a scan test data load-in input and a scan test data output of the at least one scan chain under test, and control logic operable to gate logic activity including the scan shift operation inside the integrated circuit for a single cycle when the at least one IR drop sensor outputs the first logic state and to allow normal scan test flow when the at least one IR drop sensor outputs the second logic state. There is also provided an associated method of performing at-speed scan testing of an integrated circuit.
摘要翻译：提供了包括至少一个逻辑路径的集成电路，其包括可操作地耦合到扫描链中以形成至少一个待测扫描链的多个顺序逻辑元件，至少一个IR压降传感器，可操作地耦合到集成电路电源，当所感测的电源电压低于第一预定值时，可操作以输出第一逻辑状态，并且当感测到的电源电压高于第一预定义值时输出第二逻辑状态，至少一个存储器缓冲器可操作地耦合到扫描测试数据负载输入和待测试的至少一个扫描链的扫描测试数据输出，以及当所述至少一个IR下降传感器输出时，控制逻辑可操作以对包含集成电路内的扫描移位操作的门逻辑活动进行单个周期所述第一逻辑状态并且当所述至少一个IR下降传感器输出所述第二逻辑状态时允许正常的扫描测试流程。还提供了执行集成电路的高速扫描测试的相关方法。

99. 发明申请

WO2014013293A1 SYSTEM AND METHOD FOR ON-DIE VOLTAGE DIFFERENCE MEASUREMENT ON A PASS DEVICE, AND INTEGRATED CIRCUIT 审中-公开
标题翻译：通用器件和集成电路上的电流差异测量的系统和方法
公开(公告)号：WO2014013293A1
公开(公告)日：2014-01-23
申请号：PCT/IB2012/053682
申请日：2012-07-19
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , FLESHEL, Leonid , SOFER, Sergey
发明人： PRIEL, Michael , FLESHEL, Leonid , SOFER, Sergey
IPC分类号： G05F1/565 , G05F1/10
CPC分类号： G01R19/10 , G01R31/2856
摘要： A system (12) for on-die voltage difference measurement on a pass device (14) comprises a first voltage controlled oscillator circuit (16) having a first voltage control input (18) connectable to a first terminal (20) of the pass device; a second voltage controlled oscillator circuit (22) having a second voltage control input (24) connectable to a second terminal (26) of the pass device; a first counter circuit (28) arranged to count oscillation periods of a first output signal from the first voltage controlled oscillator circuit and to provide a stop signal when a predefined number of the oscillation periods of the first output signal is counted; and a second counter circuit (30) arranged to count oscillation periods of a second output signal from the second voltage controlled oscillator circuit and to stop counting depending on the stop signal.
摘要翻译：用于通过装置（14）上的片上电压差测量的系统（12）包括第一压控振荡器电路（16），其具有可连接到通过装置的第一端子（20）的第一电压控制输入端（18） ; 具有可连接到通过装置的第二端子（26）的第二电压控制输入端（24）的第二压控振荡器电路（22）第一计数器电路（28），被布置为对来自第一压控振荡器电路的第一输出信号的振荡周期进行计数，并且当计数第一输出信号的预定数量的振荡周期时提供停止信号; 以及第二计数器电路（30），被配置为对来自第二压控振荡器电路的第二输出信号的振荡周期进行计数，并根据停止信号停止计数。

100. 发明申请

WO2013076527A1 INTEGRATED CIRCUIT, INTEGRATED CIRCUIT PACKAGE AND METHOD OF PROVIDING PROTECTION AGAINST AN ELECTROSTATIC DISCHARGE EVENT 审中-公开
标题翻译：集成电路，集成电路封装和提供防静电放电保护的方法
公开(公告)号：WO2013076527A1
公开(公告)日：2013-05-30
申请号：PCT/IB2011/055231
申请日：2011-11-22
申请人： FREESCALE SEMICONDUCTOR, INC. , SOFER, Sergey , NEIMAN, Valery , PRIEL, Michael
发明人： SOFER, Sergey , NEIMAN, Valery , PRIEL, Michael
IPC分类号： H01L23/60 , G11C5/14 , H05K9/00
CPC分类号： H01L27/0285 , H01L23/04 , H01L23/50 , H01L2924/0002 , H02H9/04 , H02H9/046 , H05K1/0259 , H01L2924/00
摘要： An integrated circuit comprising a power supply node (118), a ground node (120) and a gated domain (104) coupled between the power node (118) and the ground node. A Charged Device Model (CDM) electrostatic discharge (ESD) protection module (202) is provided for shunting electrical energy of a CDM ESD event away from the gated domain (104). A gating switch (116) is also arranged to make an electrical connection in a connected state between the gated domain (104) and at least one of the power node (118) and the ground node (120). ESD gating control circuitry (200, 216) is coupled to the CDM ESD protection module (202) and arranged to control shunting of energy away from the gated domain (104) by the CDM ESD protection module (202), thereby avoiding the energy flowing through the gated domain (104). The ESD gating control circuitry (200, 216) is arranged to inhibit actuation of the CDM ESD protection module (202) to prevent response to CDM ESD events when the gating domain (104) is being powered-up.
摘要翻译：一种集成电路，包括电源节点（118），接地节点（120）和耦合在功率节点（118）和接地节点之间的选通域（104）。提供充电装置型号（CDM）静电放电（ESD）保护模块（202），用于将远离门控域（104）的CDM ESD事件的电能分流。选通开关（116）还布置成在门控域（104）和功率节点（118）和接地节点（120）中的至少一个之间的连接状态下进行电连接。 ESD门控控制电路（200,216）耦合到CDM ESD保护模块（202），并被布置成通过CDM ESD保护模块（202）控制远离门控域（104）的能量分流，从而避免能量流动通过门控域（104）。 ESD门控控制电路（200,216）被布置成当门控域（104）上电时禁止CDM ESD保护模块（202）的致动，以防止对CDM ESD事件的响应。

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