专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2019125835A1 SYSTEM AND METHOD OF FLOATING POINT MULTIPLY OPERATION PROCESSING 审中-公开
公开(公告)号：WO2019125835A1
公开(公告)日：2019-06-27
申请号：PCT/US2018/065034
申请日：2018-12-11
申请人： QUALCOMM INCORPORATED
发明人： DANYSH, Albert , PLONDKE, Erich , MAHURIN, Eric
IPC分类号： G06F7/523 , G06F7/53
CPC分类号： G06F7/4876 , G06F7/485 , G06F7/523 , G06F7/5324
摘要： A processor includes an integer multiplier configured to execute an integer multiply instruction to multiply significand bits of at least one floating point operand of a floating point multiply operation. The processor also includes a floating point multiplier configured to execute a special purpose floating point multiply accumulate instruction with respect to an intermediate result of the floating point multiply operation and the at least one floating point operand to generate a final floating point multiplication result.

2. 发明申请

WO2008002822A2 MULPTIPLYING TWO NUMBERS 审中-公开
标题翻译：多选两个数字
公开(公告)号：WO2008002822A2
公开(公告)日：2008-01-03
申请号：PCT/US2007/071746
申请日：2007-06-21
申请人： INTEL CORPORATION , HASENPLAUGH, William , GOPAL, Vindoh , GAUBATZ, Gunnar , BACE, Matthew
发明人： HASENPLAUGH, William , GOPAL, Vindoh , GAUBATZ, Gunnar , BACE, Matthew
CPC分类号： G06F7/5324
摘要： Techniques are described to multiply two numbers, A and B. In general, multiplication is performed by using Karatsuba multiplication on the segments of A and B and adjusting the Karatsuba multiplication based on the values of the most significant bits of A and B.
摘要翻译：描述了将两个数字A和B相乘的技术。通常，乘法是通过在A和B的段上使用Karatsuba乘法并基于最显着的值调整Karatsuba乘法 A和B的位。

3. 发明申请

WO2006092448A2 VERFAHREN UND VORRICHTUNG ZUM BERECHNEN EINER POLYNOM-MULTIPLIKATION, INSBESONDERE FÜR DIE ELLIPTISCHE KURVEN-KRYPTOGRAPHIE 审中-公开
标题翻译：方法和设备用于计算多项式相乘，特别是对椭圆曲线加密
公开(公告)号：WO2006092448A2
公开(公告)日：2006-09-08
申请号：PCT/EP2006/060494
申请日：2006-03-06
申请人： IHP GMBH - INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS / INSTITUT FÜR INNOVATIVE MIKROELEKTRONIK , LANGENDOERFER, Peter , DYKA, Zoya , PETER, Steffen
发明人： LANGENDOERFER, Peter , DYKA, Zoya , PETER, Steffen
IPC分类号： G06F17/10 , G06F7/72
CPC分类号： G06F7/724 , G06F7/5324 , G06F7/725 , G06F17/10 , H04L9/3066 , H04L9/3093 , H04L2209/122 , H04L2209/80
摘要： Die Sicherung von Kommunikationskanälen ist insbesondere in drahtlosen Netzwerken erforderlich. Die Anwendung von Verschlüsselungsmechanismen in Form von Software ist durch die benötigten Berechnungs- und Energiekapazitäten mobiler Endgeräte begrenzt. Bei Verwendung von Hardware-Lösungen für kryptographische Operationen sind Kosten von Bedeutung. Die vorliegende Erfindung liefert einen Ansatz der alle diese Punkte zugleich angreift. Sie betrifft einen Hardware-Beschleuniger für die Polynom-Multiplikation in ausgedehnten Galois-Feldern (GF), wobei das an sich bekannte Karatsuba-Verfahren erfindungsgemäss iterativ angewendet wird. Bei Verwendung der Erfindung kann der Flächenbedarf beispielsweise von 6,2 mm 2 auf 2,1 mm 2 reduziert werden. Die erfindungsgemäße Lösung reduziert auch den Energieverbrauch gegenüber Lösungen nach dem Stand der Technik um 30%.
摘要翻译：通信信道的保险丝需要特别是在无线网络。以软件的形式使用加密机制是通过移动设备的需要的计算和能量的能力的限制。当使用硬件解决方案进行加密操作的成本是非常重要的。本发明提供了在同一时间攻击所有的这些点的方法。它涉及一种用于在扩展的伽罗瓦域（GF）的多项式乘法硬件加速器，本身已知的Karatsuba方法根据本发明的迭代地使用。使用本发明中，区域的要求，例如，为6.2mm ^{2 到2.1毫米^{2 可被减少。根据本发明的方案还减少了与根据由30％的现有技术解决方案相比，能量消耗。}}

4. 发明申请

WO01040934A1 PIPELINED DATA PATH CIRCUIT 审中-公开
标题翻译：管道数据路径
公开(公告)号：WO01040934A1
公开(公告)日：2001-06-07
申请号：PCT/US2000/032631
申请日：2000-11-29
IPC分类号： G06F7/52 , G06F7/533 , G06F7/544 , G06F7/57 , G06F9/30 , G06F9/302 , G06F9/38
CPC分类号： G06F7/5324 , G06F7/4991 , G06F7/49921 , G06F7/49994 , G06F7/5338 , G06F7/544 , G06F7/57 , G06F9/30014 , G06F9/30021 , G06F9/30025 , G06F9/30145 , G06F2207/382 , G06F2207/3828 , G06F2207/3884 , G06F2207/5442
摘要： A pipelined data path architecture (300) for use, in one embodiment, in a multimedia processor. The data path architecture requires a maximum of two execution pipestages to perform all instructions including wide data format multiply instructions and specially adapted multimedia instructions, such as the sum of absolute differences (SABD) instruction and other multiply with add (MADD) instructions. The data path architecture includes two wide data format input registers (310, 312) that feed four partitioned 32x32 multiplier circuits (314). Within two pipestages, the multiply circuit can perform one 128x128 multiply operation, four 32x32 multiply operations, eight 16x16 multiply operations or sixteen 8x8 multiply operations in parallel. The multiply circuit contains a compressor tree which generates a 256-bit sum (358) and a 256-bit carry (352) vector. These vectors are supplied to four 64-bit carry propagate adder circuits (340) which generate the multiply results.
摘要翻译：在一个实施例中，在多媒体处理器中使用的流水线数据路径架构（300）。数据路径架构最多需要两个执行管道来执行所有指令，包括宽数据格式乘法指令和特别适应的多媒体指令，例如绝对差（SABD）指令和其他乘以加法（MADD）指令的和。数据路径体系结构包括两个宽数据格式输入寄存器（310,312），其馈送四个分区的32×32乘法器电路（314）。在两个管道中，乘法电路可以并行执行一个128x128乘法运算，四个32x32乘法运算，八个16x16乘法运算或十八个8x8乘法运算。乘法电路包含一个生成256位和（358）和256位进位（352）矢量的压缩器树。这些矢量被提供给产生乘法结果的四个64位进位传播加法器电路（340）。

5. 发明申请

WO1993022721A1 COMPACT MULTIPLIER 审中-公开
公开(公告)号：WO1993022721A1
公开(公告)日：1993-11-11
申请号：PCT/JP1993000552
申请日：1993-04-27
申请人： SEIKO EPSON CORPORATION
发明人： SEIKO EPSON CORPORATION , CHIU, Chiao-Er, Allisa
IPC分类号： G06F07/52
CPC分类号： G06F7/5324 , A61M2210/1075 , G06F7/5338
摘要： A high-speed multiplier utilizing a layout architecture requiring very little area on a chip. The present invention employs a floor plan which exemplifies regularity and is approximately 33.3 % more compact than conventional Wallace Trees. During a first phase of a first clock cycle, Booth coding takes place resulting in a first group of partial products. In a second phase of the first clock cycle, the first group of partial products are input into a first and a second carry-save adder. Results from the second carry-save adder are latched in a first and second register. Also during the second phase of the first clock cycle, a second group of partial products are Booth coded. In a first phase of a cycle 2, the second group of partial products are input into the first and second carry-save adders. Results from the second carry-save adder are latched into a third and fourth register. In a second phase of cycle 2, results from the first, second, third and fourth registers are input into a third and fourth carry-save adder. The outputs from the fourth carry-save adder are latched into a fifth and a sixth register. In a first phase of a cycle 3, results latched in the fifth and sixth registers are input into a CPA. The CPA then generates a final output for the multiplier.
摘要翻译：利用布局架构的高速倍增器，需要芯片上极少的面积。本发明采用了比普通的华莱士树更加规模化的平面图，并且大致为33.3％。在第一时钟周期的第一阶段期间，进行Booth编码，从而产生第一组部分乘积。在第一时钟周期的第二阶段中，第一组部分积被输入到第一和第二进位加法器。来自第二进位保存加法器的结果被锁存在第一和第二寄存器中。同样在第一时钟周期的第二阶段期间，第二组部分产品被布斯编码。在循环2的第一阶段，第二组部分积被输入到第一和第二进位加载器中。第二进位保存加法器的结果被锁存到第三和第四寄存器中。在周期2的第二阶段，来自第一，第二，第三和第四寄存器的结果被输入到第三和第四进位保存加法器。来自第四进位保存加法器的输出被锁存在第五和第六寄存器中。在周期3的第一阶段，锁存在第五和第六寄存器中的结果被输入到CPA中。 CPA然后生成乘数的最终输出。

6. 发明申请

WO2012150396A3 DEVICE AND METHOD FOR FAST MULTIPLICATION 审中-公开
标题翻译：用于快速多路复用的设备和方法
公开(公告)号：WO2012150396A3
公开(公告)日：2013-01-03
申请号：PCT/FR2012050818
申请日：2012-04-13
申请人： ALTIS SEMICONDUCTOR SNC , NACCACHE DAVID , SABEG KARIM
发明人： NACCACHE DAVID , SABEG KARIM
IPC分类号： G06F7/53
CPC分类号： G06F7/5324
摘要： The present invention relates to a method of encoding an integer number using an encoding function taking as input an integer number of n words of t bits or a multiple of t bits, and outputting an ordered array U of j rows and i columns containing integers Ui,,j. The words a[k] making up the number a are intercompared in order to organise them into a series of words having an increasing value (k=0, k=1, k=2,...). An array of indices makes it possible to conserve the rank k of the word a[k] in the ordered list. A first word of a is calculated by an equation using a group of words which are not expressed as a function of other words of a. Next, all the other words of a are calculated with the aid of an equation using already calculated words. In this way, it is possible to express a large number as an ordered series of terms having small discrepancies from one another. Such encoding makes it possible to limit the number of elementary multiplications when multiplying this number with another. The present invention also relates to the circuit implementing the encoding, as well as to a circuit implementing the multiplication of numbers thus encoded.
摘要翻译：本发明涉及一种使用编码函数编码整数的方法，该编码函数将t位的n个字的整数或t位的整数作为输入，并输出包含整数U i的j行和i列的有序数组U ,,学家为了将它们组合成具有增加值的一系列词（k = 0，k = 1，k = 2，...），组合数字a的词a [k]被比较。索引数组使得有可能节省有序列表中单词a [k]的秩k。通过使用不表示为a的其他单词的函数的一组单词的方程来计算a的第一个单词。接下来，使用已经计算的单词借助于等式来计算a的所有其他单词。以这种方式，可以将大量表示为彼此具有小差异的有序序列。这样的编码使得可以在将该数乘以另一个时限制基本乘法的数量。本发明还涉及实现编码的电路，以及实现如此编码的数字相乘的电路。

7. 发明申请

WO2010101985A1 DIGITAL SIGNAL PROCESSING CIRCUITRY WITH REDUNDANCY AND BIDIRECTIONAL DATA PATHS 审中-公开
标题翻译：数字信号处理电路与冗余和双向数据处理
公开(公告)号：WO2010101985A1
公开(公告)日：2010-09-10
申请号：PCT/US2010/026023
申请日：2010-03-03
申请人： ALTERA CORPORATION , LANGHAMMER, Martin , LIN, Yi-Wen , STREICHER, Keone
发明人： LANGHAMMER, Martin , LIN, Yi-Wen , STREICHER, Keone
IPC分类号： G06F7/53
CPC分类号： H03K5/1252 , G06F7/5324 , G06F2207/382 , H03K19/17732
摘要： Digital signal processing ("DSP") circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect).
摘要翻译：提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。

8. 发明申请

WO2008002822A3 MULPTIPLYING TWO NUMBERS 审中-公开
标题翻译：复制两个数字
公开(公告)号：WO2008002822A3
公开(公告)日：2008-03-20
申请号：PCT/US2007071746
申请日：2007-06-21
申请人： INTEL CORP , HASENPLAUGH WILLIAM , GOPAL VINDOH , GAUBATZ GUNNAR , BACE MATTHEW
发明人： HASENPLAUGH WILLIAM , GOPAL VINDOH , GAUBATZ GUNNAR , BACE MATTHEW
IPC分类号： G06F7/52
CPC分类号： G06F7/5324
摘要： Techniques are described to multiply two numbers, A and B. In general, multiplication is performed by using Karatsuba multiplication on the segments of A and B and adjusting the Karatsuba multiplication based on the values of the most significant bits of A and B.
摘要翻译：技术被描述为将两个数字A和B相乘。通常，通过对A和B的段使用Karatsuba乘法来执行乘法，并且基于A和B的最高有效位的值来调整Karatsuba乘法。

9. 发明申请

WO2005010745A2 LONG-INTEGER MULTIPLIER 审中-公开
标题翻译：长整型乘法器
公开(公告)号：WO2005010745A2
公开(公告)日：2005-02-03
申请号：PCT/IB2004/002382
申请日：2004-07-22
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HUBERT, Gerardus, T., M.
发明人： HUBERT, Gerardus, T., M.
IPC分类号： G06F7/00
CPC分类号： G06F7/5318 , G06F7/509 , G06F7/5324
摘要： An adder circuit for multiplying two long integers deploys a network of adders for summing a succession of words of the long integers to generate intermediate results. The number of addends varies as a function of bit position and the network of adders is designed to reduce the number of levels of adders in the network according to a maximum number of expected addends. A number of strategically placed extra adders may be positioned in the network to further reduce the number of levels. An output stage may be provided that adds sum and carry outputs of the network and retains a most significant bit for use with a subsequent calculation output of the network. The network may be configured so that a subsequent calculation by the network can commence before the previous calculation has been completed, the output of the previous calculation being fed back to the network at an intermediate level between its highest (input) level and its lowest (output) level.
摘要翻译：用于将两个长整数相乘的加法器电路展开加法器网络，用于对长整数的一系列字进行求和以产生中间结果。加数的数量随位位置的变化而变化，加法器的网络被设计为根据预期加数的最大数量来减少网络中加法器的级数。网络中可能会放置一些战略性的额外加法器，以进一步减少级别数量。可以提供输出级，其增加网络的总和和进位输出并保留用于网络的后续计算输出的最高有效位。网络可以被配置为使得网络的后续计算可以在先前的计算已经完成之前开始，先前计算的输出在其最高（输入）电平与其最低（输入）电平之间的中间电平被反馈到网络输出）级别。

10. 发明申请

WO2003083642A2 A DATA PROCESSING SYSTEM AND METHOD FOR PERFORMING A MATHEMATICAL OPERATION ON MULTI BIT BINARY INTEGER NUMBERS USING FLOATING POINT ARITHMETIC 审中-公开
标题翻译：一种数据处理系统和方法，用于使用浮点算法对多位二进制整数进行数学运算
公开(公告)号：WO2003083642A2
公开(公告)日：2003-10-09
申请号：PCT/GB2003/001388
申请日：2003-03-28
申请人： ROBINSON, David
发明人： ROBINSON, David
IPC分类号： G06F7/00
CPC分类号： G06F7/483 , G06F7/49947 , G06F7/505 , G06F7/5324 , G06F7/72 , G06F7/723 , G06F9/30014 , G06F2207/3824
摘要： The data processing system and method performs a mathematical operation on multi bit binary integer numbers using floating point arithmetic. The binary integer numbers are divided into corresponding segments and processed to determine at least one mathematical operation product for each segment. Corresponding segments comprise a corresponding group of w bits of the binary integer numbers. Floating point registers store the products. Each floating point register has m mantissa bits, where m > w. A product sum is determined for each segment in a floating point register. A w bit result of the mathematical operation is generated in a floating point register for each segment. Also, a carry product is generated in a floating point register to be carried over to a next segment for use in the determination of the product sum for the next segment. The result and the carry product for each segment is determined by performing floating point rounding to 2 w or 2 w(i+1) on the product sum in the floating point register, where i is the segment number.
摘要翻译：数据处理系统和方法使用浮点运算对多位二进制整数进行数学运算。二进制整数被分成相应的段并被处理以确定每个段的至少一个数学运算乘积。对应的段包括二进制整数的相应的w位组。浮点寄存器存储产品。每个浮点寄存器都有m个尾数位，其中m> w。为浮点寄存器中的每个段确定乘积和。在每个段的浮点寄存器中生成数学运算的wbit结果。此外，在浮点寄存器中产生携带产品以转移到下一段，以用于确定下一段的乘积和。通过在浮点寄存器中的乘积和上执行浮点舍入为2 或2 来确定每个段的结果和进位乘积，其中i是段号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式