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1. 发明申请

WO2006019636A1 METHOD AND APPARATUS FOR DYNAMIC DLL POWERDOWN AND MEMORY SELF-REFRESH 审中-公开
标题翻译：用于动态DLL功耗和存储器自刷新的方法和装置
公开(公告)号：WO2006019636A1
公开(公告)日：2006-02-23
申请号：PCT/US2005/024375
申请日：2005-07-08
申请人： INTEL CORPORATION , SAMSON, Eric , NAVALE, Aditya , CLINE, Leslie
发明人： SAMSON, Eric , NAVALE, Aditya , CLINE, Leslie
IPC分类号： G06F1/32
CPC分类号： G06F1/3225
摘要： Embodiments of the present invention provide a method and apparatus for conserving power in an electronic device. In particular, embodiments of the present invention dynamically place the memory in self-refresh and chipset clock circuits in power down mode while keeping the isochronous streams (such as display) updated and servicing bus master cycles in a power savings mode.
摘要翻译：本发明的实施例提供了一种用于在电子设备中节省功率的方法和装置。特别地，本发明的实施例将自刷新和芯片组时钟电路中的存储器动态地放置在掉电模式中，同时保持同步流（例如显示）被更新并且在节电模式下维持总线主控周期。

2. 发明申请

WO2007030133A1 SYSTEM AND METHOD OF COHERENT DATA TRANSFER DURING PROCESSOR IDLE STATES 审中-公开
标题翻译：处理器空闲状态下的相关数据传输系统与方法
公开(公告)号：WO2007030133A1
公开(公告)日：2007-03-15
申请号：PCT/US2006/005324
申请日：2006-02-13
申请人： INTEL CORPORATION , CLINE, Leslie , SRITANYARATANA, Siripong , NAVEH, Alon , ROTEM, Efraim , SAMSON, Eric , DERR, Michael
发明人： CLINE, Leslie , SRITANYARATANA, Siripong , NAVEH, Alon , ROTEM, Efraim , SAMSON, Eric , DERR, Michael
IPC分类号： G06F12/08
CPC分类号： G06F12/0835 , G06F2212/1028 , Y02D10/13
摘要： Systems and methods of managing power provide for placing a processor in a non-snoopable state, where the processor is associated with a system memory. One or more data transfers between a controller and the system memory can be serviced while the processor is in the non-snoopable state. In one embodiment, it is determined that the processor has flushed an internal cache of the processor to the system memory before placing the processor in the non-snoopable state.
摘要翻译：管理电源的系统和方法提供将处理器置于不可窥探状态，其中处理器与系统存储器相关联。当处理器处于非可窥探状态时，可以在控制器和系统存储器之间进行一个或多个数据传输。在一个实施例中，在将处理器置于非可窥探状态之前，确定处理器将处理器的内部高速缓冲器刷新到系统存储器。

3. 发明申请

WO2013105913A2 ADAPTIVE FRAME RATE CONTROL FOR A GRAPHICS SUBSYSTEM 审中-公开
标题翻译：图形子系统的自适应帧速率控制
公开(公告)号：WO2013105913A2
公开(公告)日：2013-07-18
申请号：PCT/US2011/062501
申请日：2011-11-30
申请人： INTEL CORPORATION , RAMADOSS, Murali , SAMSON, Eric
发明人： RAMADOSS, Murali , SAMSON, Eric
IPC分类号： G06F9/06 , G06F13/14 , G06T1/00
CPC分类号： G06T1/20 , G06F1/324 , G06F1/3265 , G06F3/14 , G06T1/60 , G09G5/18 , G09G2330/021 , G09G2340/0435 , Y02D10/126 , Y02D10/153 , Y02D50/20
摘要： Examples are disclosed for adjusting a performance state of a graphics subsystem and/or a processor based on a comparison of an average frame rate to a target frame rate and also based on whether the graphics subsystem is in a burst mode or sustained mode of operation.
摘要翻译：公开了用于基于平均帧速率与目标帧速率的比较以及还基于图形子系统是否处于图像子系统和/或处理器的性能状态来调整图形子系统和/或处理器的性能状态的示例突发模式或持续操作模式。

4. 发明申请

WO2006072097A3 METHOD AND APPARATUS FOR EXTERNAL PROCESSOR THERMAL CONTROL 审中-公开
公开(公告)号：WO2006072097A3
公开(公告)日：2006-07-06
申请号：PCT/US2005/047677
申请日：2005-12-29
申请人： INTEL CORPORATION , SAMSON, Eric , HORIGAN, John , JACKSON, Robert , THAKKAR, Shreekant
发明人： SAMSON, Eric , HORIGAN, John , JACKSON, Robert , THAKKAR, Shreekant
IPC分类号： G06F1/20
摘要： A system and method for throttling a slave component of a computer system to reduce an overall temperature of the computing system upon receiving a first signal is disclosed. The first signal may be from a master component indicating that a temperature for the master component has exceeded its threshold temperature. The slave component or the master component may be a central processing unit, a graphics memory and controller hub, or a central processing unit memory controller hub. The slave component may send a second signal to indicate that a temperature for the slave component has exceeded its temperature. The master component would then initiate throttling of the master component to reduce the overall temperature of the computing system. The master component may be throttled to a degree less than the slave component. A first component may be designated the master component and the second component may be designated the slave component based on a selection policy. The selection policy may be received from a user through a graphical user interface. The selection policy may be based on an action being performed by the computing system.

5. 发明申请

WO2006072108A1 EFFICIENT Z TESTING 审中-公开
标题翻译：有效的Z测试
公开(公告)号：WO2006072108A1
公开(公告)日：2006-07-06
申请号：PCT/US2005/047690
申请日：2005-12-29
申请人： INTEL CORPORATION , PIAZZA, Thomas , SAMSON, Eric , AKAABOUNE, Nasseh , MUNAGALA, Dinakar
发明人： PIAZZA, Thomas , SAMSON, Eric , AKAABOUNE, Nasseh , MUNAGALA, Dinakar
IPC分类号： G06T15/40
CPC分类号： G06T15/405
摘要： Z testing during computer graphics rendering is performed in a manner so as to optimize rendering. The status of a pixel as non-promotable may be tracked using a pixel status array (PSA). Each PSA row may contain bits which correspond to the non-promotable status of pixels. Each row may include five pixels, the first four of which represent the pixels in a subspan. If the row corresponds to a valid subspan, a determination may be made as to whether any pixel in the subspan is represented by a one, indicating that the pixel is non-promotable. This row corresponds to a previous subspan that has been sent down rendering pipeline. If a one is present, then the current subspan may be stalled until the pixels of the previous subspan has gone through color calculation. If, in the row that has just been read, no pixels are represented by a one, then a determination may be made as to whether any pixels in the current subspan are non-promotable. If so, then the corresponding bit in the current PSA row may be set to one. Otherwise, the Z test may be performed on each pixel of the current subspan.
摘要翻译：在计算机图形渲染期间的Z测试以优化渲染的方式执行。可以使用像素状态阵列（PSA）跟踪不可升级的像素的状态。每个PSA行可以包含与像素的不可升级状态相对应的比特。每行可以包括五个像素，其中前四个表示子跨距中的像素。如果该行对应于一个有效的子跨度，则可以确定子跨越中的任何像素是否由一个表示，表示该像素是不可升级的。此行对应于已经向下渲染管道发送的先前子跨。如果存在一个，那么当前的子跨越可能会停滞，直到前一个子跨越的像素经过颜色计算。如果在刚刚读取的行中没有像素由一个像素表示，则可以确定当前子跨距中的任何像素是否不可升级。如果是，则当前PSA行中的相应位可以被设置为1。否则，可以对当前子跨的每个像素执行Z测试。

6. 发明申请

WO2020190801A1 GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY 审中-公开
公开(公告)号：WO2020190801A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/022839
申请日：2020-03-14
申请人： INTEL CORPORATION
发明人： RAY, Joydeep , PANNEER, Selvakumar , TANGRI, Saurabh , ASHBAUGH, Ben , JANUS, Scott , APPU, Abhishek , GEORGE, Varghese , IYER, Ravishankar , JAIN, Nilesh , K, Pattabhiraman , KOKER, Altug , MACPHERSON, Mike , MASTRONARDE, Josh , OULD-AHMED-VALL, Elmoustapha , S, Jayakrishna P. , SAMSON, Eric
IPC分类号： G06F9/38 , G06F12/0862 , G06F9/30 , G06F12/06
摘要： Embodiments described herein include, software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

7. 发明申请

WO2003096170A3 POWER MANAGEMENT FOR AN INTEGRATED GRAPHICS DEVICE 审中-公开
公开(公告)号：WO2003096170A3
公开(公告)日：2003-11-20
申请号：PCT/US2003/010428
申请日：2003-04-02
申请人： INTEL CORPORATION
发明人： CUI, Ying , SAMSON, Eric , BERKOVITS, Ariel , NAVALE, Aditya , WYATT, David , CLINE, Leslie , TSANG, Joseph , BLAKE, Mark , POISNER, David , STEVENS, William, Jr. , SAR-DESSAI, Vijay
IPC分类号： G06F1/32
摘要： In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) (140) through both voltage and frequency adjustment of clock signal received from a clock generator (120). The GMCH (140) comprises a graphics core (200) and a circuit (235) to alter operational behavior, such as the frequency of a render clock signal (270) supplied to the graphics core (200). The circuit (235) is adapted to monitor idleness of the graphics core (200) and reduce a frequency level of the render clock (270) signal if the idleness exceeds a determined percentage of time.

8. 发明申请

WO2016028373A1 DYNAMIC SCALING OF GRAPHICS PROCESSOR EXECUTION RESOURCES 审中-公开
标题翻译：图形处理器执行资源的动态缩放
公开(公告)号：WO2016028373A1
公开(公告)日：2016-02-25
申请号：PCT/US2015/036398
申请日：2015-06-18
申请人： INTEL CORPORATION
发明人： KABURLASOS, Nikos , SAMSON, Eric
IPC分类号： G06T1/20 , G06F11/30
CPC分类号： G06F1/3234 , G06F1/3206 , G06F1/324 , G06F1/3265 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/153 , Y02D10/171 , Y02D10/172
摘要： In one embodiment execution units, graphics cores, or graphics sub-cores can be dynamically scaled across a frame of graphics operations. Available execution units within each graphics core may be scaled using utilization metrics such as the current utilization rate of the execution units and the submission of new draw calls. In one embodiment, one of more of the sub-cores within each graphics core may be enable or disabled based on current or past utilization of the sub-cores based on a set of current graphics operations.
摘要翻译：在一个实施例中，执行单元，图形核心或图形子核心可以在图形操作的框架上动态缩放。每个图形核心中的可用执行单元可以使用诸如执行单元的当前利用率和提交新的绘制调用之类的利用度量来缩放。在一个实施例中，基于当前图形操作的集合，可以基于子核的当前或过去利用来启用或禁用每个图形核心内的多个子核中的一个。

9. 发明申请

WO2020205059A1 WORKLOAD-BASED MAXIMUM CURRENT 审中-公开
公开(公告)号：WO2020205059A1
公开(公告)日：2020-10-08
申请号：PCT/US2020/017279
申请日：2020-02-07
申请人： INTEL CORPORATION
发明人： KABURLASOS, Nikos , SAMSON, Eric , JASOLIYA, Jaymin B.
IPC分类号： G06T1/20 , G06T5/20
摘要： Described is an apparatus comprising a first circuitry and a second circuitry. The first circuitry may process a sequence of Graphics Processing Unit (GPU) commands including an instruction carrying a flag that indicates a workload characteristic corresponding with the sequence of GPU commands. The second circuitry may initiate a power-directed parameter adjustment based upon the flag.

10. 发明申请

WO2004063916A3 MEMORY CONTROLLER CONSIDERING PROCESSOR POWER STATES 审中-公开
公开(公告)号：WO2004063916A3
公开(公告)日：2004-07-29
申请号：PCT/US2004/000092
申请日：2004-01-02
申请人： INTEL CORPORATION
发明人： SAMSON, Eric , NAVALE, Aditya , JENSEN, Sam , SRITANYARATANA, Siripong , CHENG, Win
IPC分类号： G06F1/32
摘要： When a processor in a computer system is placed in a low power mode, power consumption of the computer system may be further reduced by reducing power consumption of one or more components of a memory coupled to the processor and by reducing power consumption of one or more components of a controller device coupled to the memory. The processor and the controller device may share the memory.

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