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1. 发明申请

WO2017121218A1 THIN FILM TRANSISTOR ARRAY PANEL AND CONDUCTING STRUCTURE 审中-公开
标题翻译：薄膜晶体管阵列面板和导电结构
公开(公告)号：WO2017121218A1
公开(公告)日：2017-07-20
申请号：PCT/CN2016/109559
申请日：2016-12-13
申请人： HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD. , HON HAI PRECISION INDUSTRY CO., LTD.
发明人： SHIH, Poli , KAO, Yichun , LIN, Hsinhua , LEE, Chihlung , CHANG, Weichih , LU, Imin
IPC分类号： H01L29/786 , H01L27/12 , G02F1/136
CPC分类号： H01L29/66969 , H01L21/441 , H01L21/47635 , H01L21/477 , H01L27/124 , H01L29/24 , H01L29/41733 , H01L29/45 , H01L29/458 , H01L29/66765 , H01L29/78669 , H01L29/78678 , H01L29/7869
摘要： A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that in the first sub-layer.
摘要翻译：用于薄膜晶体管（TFT）阵列面板的导电层包括限定TFT器件的源极电极和漏极电极的多层部分，并且包括第一子层，第二子层子层，第三子层和至少一个附加子层。第三和第一子层包括铟和氧化锌材料。第一子层中的铟与锌的含量比大于第三子层中的铟与锌的含量之比。在附加子层中的铟与锌的含量之比被制定在第一子层和第三子层之间。第一子层和第三子层之间的含量比例差异影响与在源极和漏极之间的第二导电层中产生的间隙相关联的横向蚀刻分布，其中第三子层中的相关联的间隙宽度比那在第一个子层。

2. 发明申请

WO2017121211A1 THIN FILM TRANSISTOR ARRAY PANEL AND CONDUCTING STRUCTURE 审中-公开
标题翻译：薄膜晶体管阵列面板和导电结构
公开(公告)号：WO2017121211A1
公开(公告)日：2017-07-20
申请号：PCT/CN2016/108892
申请日：2016-12-07
申请人： HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD. , HON HAI PRECISION INDUSTRY CO., LTD.
发明人： KAO, Yichun , LIN, Xinye , SHIH, Poli , CHANG, Weichih , LU, Yiming , WU, Iwei
IPC分类号： H01L29/12 , H01L21/77
CPC分类号： H01L29/66969 , H01L21/441 , H01L21/47635 , H01L21/477 , H01L27/124 , H01L29/24 , H01L29/41733 , H01L29/45 , H01L29/458 , H01L29/66765 , H01L29/78669 , H01L29/78678 , H01L29/7869
摘要： A thin film transistor array panel includes a first conductive layer (102) including a gate electrode; a channel layer (104) disposed over the gate; and a second conductive layer (105) disposed over the channel layer (104). The second conductive layer (105) includes a multi-layered portion defining a source electrode (105a) and a drain electrode (105b), which includes a first sub-layer (105-1), a second sub-layer (105-2), and a third sub-layer (105-3) sequentially disposed one over another. Both the third and the first sub-layers (105-3, 105-1) include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer (105-1) is greater than that in the third sub-layer (105-3). The content ratio differentiation between the first and the third sub-layers (105-1, 105-3) affects a lateral etch profile associated with a gap (106) generated in the second conductive layer (105) between the source and the drain electrodes (105a, 105b), where the associated gap (106) width in the third sub-layer (105-3) is wider than that in the first sub-layer (105-1).
摘要翻译：薄膜晶体管阵列面板包括：第一导电层（102），其包括栅电极; 布置在所述栅极上方的沟道层（104）和设置在沟道层（104）上的第二导电层（105）。第二导电层（105）包括限定源电极（105a）和漏电极（105b）的多层部分，其包括第一子层（105-1），第二子层（105-2））和第三子层（105-3），其顺序地一个在另一个之上。第三和第一子层（105-3,105-1）都包括铟和氧化锌材料。第一子层（105-1）中的铟与锌的含量比大于第三子层（105-3）中的铟与锌的含量之比。第一和第三子层（105-1,105-3）之间的含量比例区分影响与源极和漏极之间的第二导电层（105）中产生的间隙（106）相关的横向蚀刻轮廓（105a，105b），其中第三子层（105-3）中的相关间隙（106）宽度比第一子层（105-1）中的宽度更宽。

3. 发明申请

WO2017101708A1 TFT SUBSTRATE AND METHOD FOR MAKING SAME 审中-公开
标题翻译： TFT基板及其制造方法
公开(公告)号：WO2017101708A1
公开(公告)日：2017-06-22
申请号：PCT/CN2016/108670
申请日：2016-12-06
申请人： HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD. , HON HAI PRECISION INDUSTRY CO., LTD.
发明人： KAO, Yichun , SHIH, Poli , CHANG, Weichih , WU, Iwei
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78618 , H01L21/02491 , H01L27/1222 , H01L27/1225 , H01L27/124 , H01L27/1262 , H01L27/3262 , H01L29/24 , H01L29/45 , H01L29/66969 , H01L29/7869 , H01L29/78696
摘要： A high-performance TFT substrate (100) for a flat panel display includes a substrate (110), a first conductive layer (130) on the substrate (110), a semiconductor layer (103) positioned on the first conductive layer (130), and a second conductive layer (150) positioned on the semiconductor layer (103). The first conductive layer (130) defines a gate electrode (101). The second conductive layer (150) defines a source electrode (105) and a drain electrode (106) spaced apart from the source electrode (105). The second conductive layer (150) includes a first layer (151) on the semiconductor layer (103) and a second layer (152) positioned on the first layer (151). The first layer (151) can be made of metal oxide. The second layer (152) can be made of aluminum or aluminum alloy.
摘要翻译：用于平板显示器的高性能TFT基板（100）包括基板（110），位于基板（110）上的第一导电层（130），位于基板上的半导体层（103）在第一导电层（130）上，以及位于半导体层（103）上的第二导电层（150）。第一导电层（130）限定栅电极（101）。第二导电层（150）限定与源电极（105）间隔开的源电极（105）和漏电极（106）。第二导电层（150）包括在半导体层（103）上的第一层（151）和位于第一层（151）上的第二层（152）。第一层（151）可以由金属氧化物制成。第二层（152）可以由铝或铝合金制成。

4. 发明申请

WO2017121216A1 THIN FILM TRANSISTOR ARRAY PANEL 审中-公开
标题翻译：薄膜晶体管阵列面板
公开(公告)号：WO2017121216A1
公开(公告)日：2017-07-20
申请号：PCT/CN2016/109348
申请日：2016-12-10
申请人： HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD. , HON HAI PRECISION INDUSTRY CO., LTD.
发明人： KAO, Yichun , LIN, Hsinhua , SHIH, Poli , CHANG, Weichih , LU, Imin , WU, Iwei
IPC分类号： G02F1/1362 , H01L29/786
CPC分类号： G02F1/1368 , H01L29/786
摘要： A semiconductor device comprises a multi-layered structure disposed over a substrate (101) and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer (105-1) disposed over the substrate (101) and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the lower sub-layer (105-1) substantially defining a first indium to zinc content ratio; a middle sub-layer (105-2) disposed over the lower sub-layer (105-1) and comprising a metal material; an upper sub-layer (105-3) disposed over the middle sub-layer (105-2) and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer (105-3) substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer (105-2).
摘要翻译：半导体器件包括设置在衬底（101）上方并限定复合横向蚀刻轮廓的多层结构。多层结构包括设置在衬底（101）上方的下部子层（105-1），并且包括包含铟和锌的金属氧化物材料，下部子层（105-1）中的铟和锌含量）基本上限定第一铟与锌的含量比率; 设置在所述下子层（105-1）上并包含金属材料的中间子层（105-2）设置在所述中间子层（105-2）上并且包括金属氧化物材料的上子层（105-3），所述金属氧化物材料包括铟和锌，所述上子层（105-3）中的铟至锌含量，基本上限定小于所述第一铟与锌含量比的第二铟与锌含量比; 以及形成在横向刻蚀表面上的横向副产物层，基本上包括中间子层（105-2）中的金属材料的金属氧化物。

5. 发明申请

WO2017121215A1 METHOD FOR FABRICATING CONDUCTING STRUCTURE AND THIN FILM TRANSISTOR ARRAY PANEL 审中-公开
标题翻译：制作导电结构和薄膜晶体管阵列面板的方法
公开(公告)号：WO2017121215A1
公开(公告)日：2017-07-20
申请号：PCT/CN2016/109347
申请日：2016-12-10
申请人： HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD. , HON HAI PRECISION INDUSTRY CO., LTD.
发明人： LIN, Hsinhua , SHIH, Poli , KAO, Yichun , WAN, Changchun , CHANG, Weichih , WU, Iwei
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/66969 , H01L21/441 , H01L21/47635 , H01L21/477 , H01L27/124 , H01L29/24 , H01L29/41733 , H01L29/45 , H01L29/458 , H01L29/66765 , H01L29/78669 , H01L29/78678 , H01L29/7869
摘要： A method of providing a conducting structure over a substrate, which comprises: disposing a lower sub-layer over a substrate, the lower sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and zinc content in the bottom sub-layer substantially defines a first indium to zinc content ratio; performing a first hydrogen treatment over an exposed surface of the lower sub-layer for introducing hydrogen content therein; disposing a middle sub-layer over the lower sub-layer, the middle sub-layer comprising a metal material; disposing an upper sub-layer over the middle sub-layer, the upper sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and the zinc content in the upper sub-layer substantially defines a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and patterning the multi-layered conductive structure to generate a composite lateral etch profile.
摘要翻译：一种在衬底上提供导电结构的方法，其包括：在衬底上设置下子层，所述下子层包括包含铟和锌的导电金属氧化物材料，其中底部子层中的铟和锌含量基本上限定了第一铟与锌含量比; 在所述下子层的暴露表面上进行第一氢处理以在其中引入氢含量; 在所述下子层上设置中间子层，所述中间子层包括金属材料; 在所述中间子层上设置上子层，所述上子层包括包含铟和锌的导电金属氧化物材料，其中所述上子层中的铟和锌含量基本上限定第二铟至锌含量比小于第一铟与锌的含量比; 并图案化多层导电结构以产生复合横向蚀刻轮廓。

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