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1. 发明申请

WO2012087561A3 SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTEM TO AUTOMATICALLY DECOMPOSE A PROGRAM TO MULTIPLE PARALLEL THREADS 审中-公开
标题翻译：硬件和软件系统自动将程序分解为多个并行线程的系统，装置和方法
公开(公告)号：WO2012087561A3
公开(公告)日：2012-08-16
申请号：PCT/US2011063466
申请日：2011-12-06
申请人： INTEL CORP , SAGER DAVID J , SASANKA RUCHIRA , GABOR RON , RAIKIN SHLOMO , NUZMAN JOSEPH , PELED LEEOR , DOMER JASON A , KIM HO-SEOP , WU YOUFENG , YAMADA KOICHI , NGAI TIN-FOOK , CHEN HOWARD H , BOBBA JAYARAM , COOK JEFFREY J , SHAIKH OSMAR M , SRINIVAS SURESH
发明人： SAGER DAVID J , SASANKA RUCHIRA , GABOR RON , RAIKIN SHLOMO , NUZMAN JOSEPH , PELED LEEOR , DOMER JASON A , KIM HO-SEOP , WU YOUFENG , YAMADA KOICHI , NGAI TIN-FOOK , CHEN HOWARD H , BOBBA JAYARAM , COOK JEFFREY J , SHAIKH OSMAR M , SRINIVAS SURESH
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F8/4442 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/54 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2213/0038
摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
摘要翻译：描述了用于将程序自动分解成多个并行线程的硬件和软件系统的系统，设备和方法。在一些实施例中，系统和设备执行原始代码分解和/或生成的线程执行的方法。

2. 发明申请

WO2012087561A2 SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTEM TO AUTOMATICALLY DECOMPOSE A PROGRAM TO MULTIPLE PARALLEL THREADS 审中-公开
标题翻译：用于硬件和软件系统的系统，设备和方法，用于自动将程序分解成多个并行线程
公开(公告)号：WO2012087561A2
公开(公告)日：2012-06-28
申请号：PCT/US2011/063466
申请日：2011-12-06
申请人： INTEL CORPORATION , SAGER, David J. , SASANKA, Ruchira , GABOR, Ron , RAIKIN, Shlomo , NUZMAN, Joseph , PELED, Leeor , DOMER, Jason A. , KIM, Ho-Seop , WU, Youfeng , YAMADA, Koichi , NGAI, Tin-Fook , CHEN, Howard H. , BOBBA, Jayaram , COOK, Jeffrey J. , SHAIKH, Osmar M. , SRINIVAS, Suresh
发明人： SAGER, David J. , SASANKA, Ruchira , GABOR, Ron , RAIKIN, Shlomo , NUZMAN, Joseph , PELED, Leeor , DOMER, Jason A. , KIM, Ho-Seop , WU, Youfeng , YAMADA, Koichi , NGAI, Tin-Fook , CHEN, Howard H. , BOBBA, Jayaram , COOK, Jeffrey J. , SHAIKH, Osmar M. , SRINIVAS, Suresh
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F8/4442 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/54 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2213/0038
摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
摘要翻译：描述了用于将程序自动分解为多个并行线程的硬件和软件系统的系统，装置和方法。在一些实施例中，系统和装置执行原始代码分解和/或生成的线程执行的方法。

3. 发明申请

WO2014137327A1 ANALYZING POTENTIAL BENEFITS OF VECTORIZATION 审中-公开
标题翻译：分析潜在的收益优势
公开(公告)号：WO2014137327A1
公开(公告)日：2014-09-12
申请号：PCT/US2013/029165
申请日：2013-03-05
申请人： INTEL CORPORATION , SASANKA, Ruchira , COOK, Jeffrey J. , DAS, Abhinav , BOBBA, Jayaram , GREENFIELD, Michael R. , SRINIVAS, Suresh
发明人： SASANKA, Ruchira , COOK, Jeffrey J. , DAS, Abhinav , BOBBA, Jayaram , GREENFIELD, Michael R. , SRINIVAS, Suresh
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F8/41 , G06F8/456
摘要： Embodiments of computer-implemented methods, systems, computing devices, and computer-readable media (transitory and non-transitory) are described herein for analyzing execution of a plurality of executable instructions and, based on the analysis, providing an indication of a benefit to be obtained by vectorization of at least a subset of the plurality of executable instructions. In various embodiments, the analysis may include identification of the subset of the plurality of executable instructions suitable for conversion to one or more single-instruction multiple-data ("SIMD") instructions.
摘要翻译：本文描述了计算机实现的方法，系统，计算设备和计算机可读介质（暂时性和非暂时性）的实施例，用于分析多个可执行指令的执行，并且基于该分析，提供对可以通过对多个可执行指令的至少一个子集进行向量化来获得。在各种实施例中，分析可以包括适合于转换为一个或多个单指令多数据（“SIMD”）指令的多个可执行指令的子集的标识。

4. 发明申请

WO2013147868A1 HARDWARE PROFILING MECHANISM TO ENABLE PAGE LEVEL AUTOMATIC BINARY TRANSLATION 审中-公开
标题翻译：硬件配置机制启用页面级自动二进制翻译
公开(公告)号：WO2013147868A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/031572
申请日：2012-03-30
申请人： INTEL CORPORATION , CAPRIOLI, Paul , MERTEN, Matthew C. , AL-OTOOM, Muawya M. , SHAIKH, Omar M. , KANHERE, Abhay S. , SRINIVAS, Suresh , YAMADA, Koichi , THAKKAR, Vivek , OSCIAK, Pawel
发明人： CAPRIOLI, Paul , MERTEN, Matthew C. , AL-OTOOM, Muawya M. , SHAIKH, Omar M. , KANHERE, Abhay S. , SRINIVAS, Suresh , YAMADA, Koichi , THAKKAR, Vivek , OSCIAK, Pawel
IPC分类号： G06F15/80 , G06F9/30 , G06F13/14
CPC分类号： G06F11/3466 , G06F8/40 , G06F8/52 , G06F9/3017 , G06F9/3842 , G06F9/4552 , G06F11/073 , G06F11/3616 , G06F11/3652
摘要： A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.
摘要翻译：通过性能监控硬件实现的硬件剖析机制可实现页面级自动二进制翻译。运行期间的硬件标识内存中包含潜在优化指令的代码页。硬件请求与代码页相关联的内存中的新页面的分配，其中新页面包含计数器的集合，并且每个计数器对应于代码页中的指令之一。当硬件检测到在代码页内具有分支目标的分支指令时，它增加与代码页中的分支目标相同的新页面中具有相同位置的计数器之一。代码页的执行被重复，并且当分支目标落在代码页内时计数器递增。然后硬件将新页面中的计数器值提供给用于二进制转换的二进制转换器。

5. 发明申请

WO2013048468A1 INSTRUCTION AND LOGIC TO PERFORM DYNAMIC BINARY TRANSLATION 审中-公开
标题翻译：指令和逻辑执行动态二进制翻译
公开(公告)号：WO2013048468A1
公开(公告)日：2013-04-04
申请号：PCT/US2011/054380
申请日：2011-09-30
申请人： INTEL CORPORATION , KANHERE, Abhay, S. , CAPRIOLI, Paul , YAMADA, Koichi , MADRAS-SUBRAMANIAN, Suriya , SRINIVAS, Suresh
发明人： KANHERE, Abhay, S. , CAPRIOLI, Paul , YAMADA, Koichi , MADRAS-SUBRAMANIAN, Suriya , SRINIVAS, Suresh
IPC分类号： G06F9/45
CPC分类号： G06F8/40 , G06F8/456 , G06F8/51 , G06F9/30109 , G06F9/30185 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3877 , G06F9/3887 , G06F9/4552
摘要： A micro-architecture may provide a hardware and software co-designed dynamic binary translation. The micro-architecture may invoke a method to perform a dynamic binary translation. The method may comprise executing original software code compiled targeting a first instruction set, using processor hardware to detect a hot spot in the software code and passing control to a binary translation translator, determining a hot spot region for translation, generating the translated code using a second instruction set, placing the translated code in a translation cache, executing the translated code from the translated cache, and transitioning back to the original software code after the translated code finishes execution.
摘要翻译：微架构可以提供硬件和软件协同设计的动态二进制翻译。微架构可以调用执行动态二进制转换的方法。该方法可以包括执行针对第一指令集编译的原始软件代码，使用处理器硬件来检测软件代码中的热点并将控制传递给二进制翻译翻译器，确定用于翻译的热点区域，使用第二指令集，将转换的代码放置在转换高速缓存中，从翻译的高速缓存中执行转换的代码，并且在转换的代码完成执行之后转换回原始软件代码。

6. 发明申请

WO2007078920A1 METHOD AND APPARATUS FOR HARDWARE-BASED DYNAMIC ESCAPE DETECTION IN MANAGED RUN-TIME ENVIRONMENTS 审中-公开
标题翻译：管理运行环境中基于硬件的动态ESCAPE检测的方法与装置
公开(公告)号：WO2007078920A1
公开(公告)日：2007-07-12
申请号：PCT/US2006/048278
申请日：2006-12-18
申请人： INTEL CORPORATION , JACOBSON, Quinn, A. , SRINIVAS, Suresh , BRACY, Anne, C. , WANG, Hong
发明人： JACOBSON, Quinn, A. , SRINIVAS, Suresh , BRACY, Anne, C. , WANG, Hong
IPC分类号： G06F12/02
CPC分类号： G06F12/0802 , G06F12/0269
摘要： A method and apparatus for hardware-based dynamic escape detection in managed run-time environments are described. In one embodiment, the method includes the detection of a pointer update of a first object having a global scope. In one embodiment, a single instruction is issued to assert that a scope attribute associated with a target object of the pointer update identifies a global scope. The single instruction may return failure if the scope attribute that is associated with the second object identifies the scope of the second object as local. Verification may include the reading of an object descriptor for the second object to determine whether a scope attribute of the object descriptor indicates that the scope of the second object is local. Once verified, in one embodiment, the second object, and each object reachable from the second object, are converted into global objects. Other embodiments are described and claimed.
摘要翻译：描述了在受管理的运行时环境中用于基于硬件的动态逃逸检测的方法和装置。在一个实施例中，该方法包括检测具有全局范围的第一对象的指针更新。在一个实施例中，发出单个指令以断言与指针更新的目标对象相关联的范围属性标识全局范围。如果与第二个对象相关联的范围属性将第二个对象的范围标识为本地，那么单个指令可能会返回失败。验证可以包括读取第二对象的对象描述符，以确定对象描述符的范围属性是否指示第二对象的范围是本地的。一旦验证，在一个实施例中，第二对象和从第二对象可访问的每个对象被转换成全局对象。描述和要求保护其他实施例。

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