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1. 发明申请

WO2012087561A3 SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTEM TO AUTOMATICALLY DECOMPOSE A PROGRAM TO MULTIPLE PARALLEL THREADS 审中-公开
标题翻译：硬件和软件系统自动将程序分解为多个并行线程的系统，装置和方法
公开(公告)号：WO2012087561A3
公开(公告)日：2012-08-16
申请号：PCT/US2011063466
申请日：2011-12-06
申请人： INTEL CORP , SAGER DAVID J , SASANKA RUCHIRA , GABOR RON , RAIKIN SHLOMO , NUZMAN JOSEPH , PELED LEEOR , DOMER JASON A , KIM HO-SEOP , WU YOUFENG , YAMADA KOICHI , NGAI TIN-FOOK , CHEN HOWARD H , BOBBA JAYARAM , COOK JEFFREY J , SHAIKH OSMAR M , SRINIVAS SURESH
发明人： SAGER DAVID J , SASANKA RUCHIRA , GABOR RON , RAIKIN SHLOMO , NUZMAN JOSEPH , PELED LEEOR , DOMER JASON A , KIM HO-SEOP , WU YOUFENG , YAMADA KOICHI , NGAI TIN-FOOK , CHEN HOWARD H , BOBBA JAYARAM , COOK JEFFREY J , SHAIKH OSMAR M , SRINIVAS SURESH
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F8/4442 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/54 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2213/0038
摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
摘要翻译：描述了用于将程序自动分解成多个并行线程的硬件和软件系统的系统，设备和方法。在一些实施例中，系统和设备执行原始代码分解和/或生成的线程执行的方法。

2. 发明申请

WO2012087561A2 SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTEM TO AUTOMATICALLY DECOMPOSE A PROGRAM TO MULTIPLE PARALLEL THREADS 审中-公开
标题翻译：用于硬件和软件系统的系统，设备和方法，用于自动将程序分解成多个并行线程
公开(公告)号：WO2012087561A2
公开(公告)日：2012-06-28
申请号：PCT/US2011/063466
申请日：2011-12-06
申请人： INTEL CORPORATION , SAGER, David J. , SASANKA, Ruchira , GABOR, Ron , RAIKIN, Shlomo , NUZMAN, Joseph , PELED, Leeor , DOMER, Jason A. , KIM, Ho-Seop , WU, Youfeng , YAMADA, Koichi , NGAI, Tin-Fook , CHEN, Howard H. , BOBBA, Jayaram , COOK, Jeffrey J. , SHAIKH, Osmar M. , SRINIVAS, Suresh
发明人： SAGER, David J. , SASANKA, Ruchira , GABOR, Ron , RAIKIN, Shlomo , NUZMAN, Joseph , PELED, Leeor , DOMER, Jason A. , KIM, Ho-Seop , WU, Youfeng , YAMADA, Koichi , NGAI, Tin-Fook , CHEN, Howard H. , BOBBA, Jayaram , COOK, Jeffrey J. , SHAIKH, Osmar M. , SRINIVAS, Suresh
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F8/4442 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/54 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2213/0038
摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
摘要翻译：描述了用于将程序自动分解为多个并行线程的硬件和软件系统的系统，装置和方法。在一些实施例中，系统和装置执行原始代码分解和/或生成的线程执行的方法。

3. 发明申请

WO2013095467A1 A BALANCED P-LRU TREE FOR A "MULTIPLE OF 3" NUMBER OF WAYS CACHE 审中-公开
标题翻译：一个平衡的P-LRU树，一个“多个3”的方式高速缓存
公开(公告)号：WO2013095467A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066652
申请日：2011-12-21
申请人： INTEL CORPORATION , BASEL, Adi , HILDESHEIM, Gur , RAIKIN, Shlomo , CHAPPELL, Robert , KIM, Ho-Seop , BHATIA, Rohit
发明人： BASEL, Adi , HILDESHEIM, Gur , RAIKIN, Shlomo , CHAPPELL, Robert , KIM, Ho-Seop , BHATIA, Rohit
IPC分类号： G06F1/00
CPC分类号： G06F12/122 , G06F3/0604 , G06F12/00 , G06F12/0842 , G06F12/0864 , G06F12/124 , G06F12/125
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a "multiple of 3" number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways. In this exemplary embodiment, the total number of bits is N-1, wherein N is the total number of ways in the plurality of ways. Alternative structures are also presented for full LRU implementation, a "multiple of 5" number of cache ways, and variations of the "multiple of 3" number of cache ways.
摘要翻译：根据本文公开的实施例，提供了用于实现用于“3”倍的方式高速缓存的平衡P-LRU树的方法，系统，机制，技术和装置。例如，在一个实施例中，这种装置可以包括具有高速缓存和多个方式的集成电路。在这样的实施例中，多个方式包括一个数量是三的倍数，而不是二的幂，并且其中多个方式被组织成多对。在这样的实施例中，装置还包括用于多个对中的每一对的单个位，其中每个单个位将用作表示相关联的方式的中间级决策节点和具有正好两个单独位的根级判定节点指向要作为表示相关联的方式的中间级决策节点操作的单个位之一。在该示例性实施例中，总数是N-1，其中N是多个方式的总路数。还提供了替代结构，用于完整的LRU实现，“多路复用5”缓存方式，以及“3”倍数缓存方式的变化。

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