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1. 发明授权

US10615781B2 Semiconductor apparatus 有权
公开(公告)号：US10615781B2
公开(公告)日：2020-04-07
申请号：US16517188
申请日：2019-07-19
申请人： SK hynix Inc.
发明人： Young Hoon Kim
IPC分类号： H03K25/00 , H03K3/027 , H03K5/151 , H03K5/1252 , H03K3/012 , H03K3/356 , H03K19/0175
CPC分类号： H03K3/027 , H03K3/012 , H03K3/356043 , H03K5/1252 , H03K5/151 , H03K19/0175
摘要： A semiconductor apparatus includes a pulse generation circuit which generates a pulse signal in response to a clock, and an amplification circuit which generates an output signal in response to an input signal, the clock, and the pulse signal, wherein the amplification circuit voltage is configured to amplify a voltage level difference between a pair of latch input nodes.

2. 发明授权

US09966963B2 Frequency synthesizer 有权
公开(公告)号：US09966963B2
公开(公告)日：2018-05-08
申请号：US15273746
申请日：2016-09-23
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Mao-Hsuan Chou , Chih-Chiang Chang , Chung-Chieh Yang
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00 , H03L7/099 , H03L7/181
CPC分类号： H03L7/0991 , H03L7/18 , H03L7/181 , H03L2207/50
摘要： A frequency synthesizer comprising a reference oscillator configured to generate a first clock signal with a reference frequency and a divider controller configured to receive the first clock signal, a second clock signal, and a multiplier value. The divider controller is configured to obtain a ratio of a frequency of the first clock signal to a frequency of the second clock signal and divide the resulting ratio by the multiplier value to obtain controller output value. A divider is configured to receive the first clock signal and controller output value and output an output clock signal with a frequency equal to the frequency of the first clock signal divided by the controller output value.

3. 发明授权

US08917122B1 Frequency dividers 有权
标题翻译：分频器
公开(公告)号：US08917122B1
公开(公告)日：2014-12-23
申请号：US14019875
申请日：2013-09-06
申请人： Infineon Technologies AG
发明人： Heiko Koerner
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00 , H03K21/02
CPC分类号： H03K21/026 , H03K21/10
摘要： Various embodiments relate to frequency dividers. A current of a current source of the frequency divider is controlled based on a property of an output signal of the frequency divider.
摘要翻译：各种实施例涉及分频器。基于分频器的输出信号的特性来控制分频器的电流源的电流。

4. 发明授权

US08884663B2 State machine for low-noise clocking of high frequency clock 有权
标题翻译：高频时钟低噪声时钟状态机
公开(公告)号：US08884663B2
公开(公告)日：2014-11-11
申请号：US13776489
申请日：2013-02-25
申请人： Advanced Micro Devices, Inc.
发明人： Steven J. Kommrusch , Zihno Jusufovic
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00 , H03K21/02
CPC分类号： H03K21/023 , G06F1/10 , H03K5/135 , H03K19/00346
摘要： Methods, apparatus, and fabrication techniques relating to management of noise arising from capacitance in a clock tree of an integrated circuit. In some embodiments, the methods comprise receiving a signal to adjust a clock having a first rate to a second rate; and ramping, in response to receiving the signal, the clock from the first rate to the second rate, wherein the ramping comprises changing the frequency of the clock to at least one third rate between the first and second rates.
摘要翻译：与集成电路的时钟树中由电容产生的噪声的管理相关的方法，装置和制造技术。在一些实施例中，所述方法包括接收信号以将具有第一速率的时钟调整到第二速率; 并且响应于接收到所述信号而将所述时钟从所述第一速率斜升到所述第二速率，其中所述斜坡包括将所述时钟的频率改变为所述第一和第二速率之间的至少三分之一速率。

5. 发明授权

US08633722B1 Method and circuit for testing accuracy of delay circuitry 有权
标题翻译：用于测试延迟电路精度的方法和电路
公开(公告)号：US08633722B1
公开(公告)日：2014-01-21
申请号：US12894026
申请日：2010-09-29
申请人： Andrew W. Lai
发明人： Andrew W. Lai
IPC分类号： G01R31/3187 , G01R31/20 , H03K25/00 , G01R31/28
CPC分类号： G01R31/2882 , G01R31/31725 , H03K19/17764 , H03K23/425
摘要： In one embodiment a circuit for testing delays is provided. A test signal generator circuit toggles a plurality of output signals 1 through N in sequential order, separating the toggles by a delay period. Each output signal is coupled to an input of a respective one of a plurality of delay circuits. A phase detector circuit is coupled to the delay circuits and is configured to determine the order in which signals output from delay circuits X−1, X, and X+1 are toggled for each delay circuit X. In response to the output signals being toggled in the order X−1 followed by X followed by X+1, the phase comparator circuit is configured to output a first signal indicating correct operation. Otherwise, the phase comparator circuit is configured to output a second signal indicating incorrect operation.
摘要翻译：在一个实施例中，提供了用于测试延迟的电路。测试信号发生器电路按顺序切换多个输出信号1至N，将切换分开延迟时间。每个输出信号耦合到多个延迟电路中的相应一个的输入。相位检测器电路被耦合到延迟电路，并且被配置为确定从延迟电路X-1，X和X + 1输出的信号针对每个延迟电路X切换的顺序。响应于输出信号被切换按照X-1之后的X，随后是X + 1，相位比较器电路被配置为输出指示正确操作的第一信号。否则，相位比较器电路被配置为输出指示不正确操作的第二信号。

6. 发明授权

US08531213B2 CMOS-inverter-type frequency divider circuit, and mobile phone including the CMOS-inverter-type frequency divider circuit 有权
标题翻译： CMOS逆变型分频电路，以及手机包括CMOS逆变型分频电路
公开(公告)号：US08531213B2
公开(公告)日：2013-09-10
申请号：US13321009
申请日：2010-04-08
申请人： Masakatsu Maeda , Mikihiro Shimada
发明人： Masakatsu Maeda , Mikihiro Shimada
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00
CPC分类号： H03K23/68 , G06F7/68 , H03K23/667
摘要： The present invention provides a CMOS-inverter-type frequency divider circuit that can further reduce power consumption.The CMOS-inverter-type frequency divider circuit includes: a plurality of CMOS inverters that contribute to realizing a frequency division function; a frequency division control section for performing control such that some or all of the plurality of CMOS inverters are intermittently driven at the respective different timings in accordance with an input signal; and a drive power supplying section for supplying powers for driving the plurality of CMOS inverters, and for, based on state information indicating whether VCO sub band selection or normal transmission is performed, switching some or all of the powers for the plurality of CMOS inverters between the VCO sub band selection and the normal transmission.
摘要翻译：本发明提供一种可以进一步降低功耗的CMOS反相器型分频器电路。 CMOS反相器型分频器电路包括：有助于实现分频功能的多个CMOS反相器; 分频控制部分，用于执行控制，使得多个CMOS反相器中的一些或全部根据输入信号在各个不同的定时被间歇地驱动; 以及用于提供用于驱动多个CMOS反相器的电力的驱动电力供应部分，并且基于指示是否执行VCO子带选择还是正常传输的状态信息，将多个CMOS反相器的部分或全部功率切换到 VCO子频段选择和正常传输。

7. 发明授权

US08248118B2 High-speed frequency divider and a phase locked loop that uses the high-speed frequency divider 有权
公开(公告)号：US08248118B2
公开(公告)日：2012-08-21
申请号：US12852520
申请日：2010-08-09
申请人： Karthik Subburaj , Dhanya K
发明人： Karthik Subburaj , Dhanya K
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00
CPC分类号： H03L7/18 , H03K23/667 , H03L2207/50
摘要： A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage in the plurality of divider stages is coupled to receive the first frequency-divided signal and to generate the first mode signal. The output stage receives the output mode signal and a control signal, and generates an output signal by dividing a frequency of the output mode signal by two if the control signal is at one logic level. The output stage forwards the output mode signal without division otherwise.

8. 发明授权

US08067959B2 Programmable delay line compensated for process, voltage, and temperature 有权
标题翻译：可编程延迟线补偿过程，电压和温度
公开(公告)号：US08067959B2
公开(公告)日：2011-11-29
申请号：US12716469
申请日：2010-03-03
申请人： William C. Plants , Suhail Zain , Joel Landry , Gregory W. Bakker , Tomek P. Jasinoski
发明人： William C. Plants , Suhail Zain , Joel Landry , Gregory W. Bakker , Tomek P. Jasinoski
IPC分类号： H03K19/173 , H03K25/00
CPC分类号： H03K5/131 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143 , H03K2005/00156 , H03L7/07 , H03L7/0805 , H03L7/0814 , H03L7/10
摘要： A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.
摘要翻译：补偿过程，电压和温度变化的延迟线包括被配置为将数字信号延迟数字信号的时钟周期的延迟锁定环（DLL），该DLL包括布置为多个级联子串的DLL延迟线为了响应于数字控制信号，延迟每个子延迟线提供多个延迟量子中的一个。分馏电路被配置为产生作为数字控制信号的一部分的数字延迟线控制信号。数字延迟线被布置为多个级联子延迟线，每个子延迟线响应于数字延迟线控制信号提供多个延迟量子中的一个。

9. 发明授权

US07656204B2 Divider circuit 有权
标题翻译：分频电路
公开(公告)号：US07656204B2
公开(公告)日：2010-02-02
申请号：US11713544
申请日：2007-03-02
申请人： Stephan Henzler , Siegmar Koeppe
发明人： Stephan Henzler , Siegmar Koeppe
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00
CPC分类号： H03K3/356191 , H03K3/012 , H03K5/00006 , H03K5/15013 , H03K2005/00286
摘要： A divider circuit comprises at least two clock edge controlled differential buffer store elements, each being clocked by complementary input clock signals, each comprising internal storage nodes which are pre-chargeable to a pre-charge potential, and each comprising a differential data input. The internal storage nodes of the buffer store elements are either pre-charged at the pre-charge potential or store a logic level, depending on the relevant input clock signals. The differential data inputs of one of the buffer store elements is connected to the internal storage nodes of the other buffer store element and pulsed signals can be tapped off at the internal differential storage node.
摘要翻译：分频器电路包括至少两个时钟沿控制的差分缓冲器存储器元件，每个元件由互补的输入时钟信号计时，每个时钟信号包括可预充电到预充电电位的内部存储节点，并且每个包括差分数据输入。缓冲存储器元件的内部存储节点或者是以预充电电位预充电，或根据相关的输入时钟信号存储逻辑电平。缓冲存储元件之一的差分数据输入连接到另一个缓冲存储元件的内部存储节点，并且脉冲信号可以在内部差分存储节点被分接。

10. 发明授权

US07600167B2 Flip-flop, shift register, and scan test circuit 失效
标题翻译：触发器，移位寄存器和扫描测试电路
公开(公告)号：US07600167B2
公开(公告)日：2009-10-06
申请号：US11727451
申请日：2007-03-27
申请人： Hiroaki Shoda
发明人： Hiroaki Shoda
IPC分类号： G01R31/28 , G01R31/26 , G06F1/00 , G11C29/00 , H03K3/289 , H03K3/00 , H03K5/13 , H03H11/16 , H03K19/00 , H03K21/00 , H03K23/00 , H03K25/00 , H03K3/02
CPC分类号： G01R31/318541
摘要： A flip-flop has a first latch and a second latch. The first latch has a first feedback circuit and a first selecting circuit which selects one of a first data input signal and an output signal of the first feedback circuit, based on the logic level of a first clock signal. The second latch has a second feedback circuit and a second selecting circuit which selects an output signal of the first latch and an output signal of the second feedback circuit based on the inverted logic level in case of the first latch. The first feedback circuit has a third selecting circuit which selects one of an output signal of the first latch and a second data input signal based on the logic level of a second clock signal, and outputs a signal selected by the third selecting circuit to the first selecting circuit.
摘要翻译：触发器具有第一锁存器和第二锁存器。第一锁存器具有基于第一时钟信号的逻辑电平的第一反馈电路和第一选择电路，其选择第一反馈电路的第一数据输入信号和输出信号之一。第二锁存器具有第二反馈电路和第二选择电路，其在第一锁存器的情况下基于反相逻辑电平选择第一锁存器的输出信号和第二反馈电路的输出信号。第一反馈电路具有第三选择电路，其基于第二时钟信号的逻辑电平选择第一锁存器的输出信号和第二数据输入信号中的一个，并将由第三选择电路选择的信号输出到第一选择电路。

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