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1. 发明授权

US08067959B2 Programmable delay line compensated for process, voltage, and temperature 有权
标题翻译：可编程延迟线补偿过程，电压和温度
公开(公告)号：US08067959B2
公开(公告)日：2011-11-29
申请号：US12716469
申请日：2010-03-03
申请人： William C. Plants , Suhail Zain , Joel Landry , Gregory W. Bakker , Tomek P. Jasinoski
发明人： William C. Plants , Suhail Zain , Joel Landry , Gregory W. Bakker , Tomek P. Jasinoski
IPC分类号： H03K19/173 , H03K25/00
CPC分类号： H03K5/131 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143 , H03K2005/00156 , H03L7/07 , H03L7/0805 , H03L7/0814 , H03L7/10
摘要： A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.
摘要翻译：补偿过程，电压和温度变化的延迟线包括被配置为将数字信号延迟数字信号的时钟周期的延迟锁定环（DLL），该DLL包括布置为多个级联子串的DLL延迟线为了响应于数字控制信号，延迟每个子延迟线提供多个延迟量子中的一个。分馏电路被配置为产生作为数字控制信号的一部分的数字延迟线控制信号。数字延迟线被布置为多个级联子延迟线，每个子延迟线响应于数字延迟线控制信号提供多个延迟量子中的一个。

2. 发明申请

US20100156459A1 PROGRAMMABLE DELAY LINE COMPENSATED FOR PROCESS, VOLTAGE, AND TEMPERATURE 有权
标题翻译：可编程延迟线补偿过程，电压和温度
公开(公告)号：US20100156459A1
公开(公告)日：2010-06-24
申请号：US12716469
申请日：2010-03-03
申请人： William C. Plants , Suhail Zain , Joel Landry , Gregory W. Bakker , Tomek P. Jasionowski
发明人： William C. Plants , Suhail Zain , Joel Landry , Gregory W. Bakker , Tomek P. Jasionowski
IPC分类号： H03K19/177 , H03L7/06
CPC分类号： H03K5/131 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143 , H03K2005/00156 , H03L7/07 , H03L7/0805 , H03L7/0814 , H03L7/10
摘要： A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.
摘要翻译：补偿过程，电压和温度变化的延迟线包括被配置为将数字信号延迟数字信号的时钟周期的延迟锁定环（DLL），该DLL包括布置为多个级联子串的DLL延迟线为了响应于数字控制信号，延迟每个子延迟线提供多个延迟量子中的一个。分馏电路被配置为产生作为数字控制信号的一部分的数字延迟线控制信号。数字延迟线被布置为多个级联子延迟线，每个子延迟线响应于数字延迟线控制信号提供多个延迟量子中的一个。

3. 发明授权

US07701246B1 Programmable delay line compensated for process, voltage, and temperature 失效
标题翻译：可编程延迟线补偿过程，电压和温度
公开(公告)号：US07701246B1
公开(公告)日：2010-04-20
申请号：US12175399
申请日：2008-07-17
申请人： William C. Plants , Suhail Zain , Joel Landry , Gregory W. Bakker , Tomek Jasionowski
发明人： William C. Plants , Suhail Zain , Joel Landry , Gregory W. Bakker , Tomek Jasionowski
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K5/131 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143 , H03K2005/00156 , H03L7/07 , H03L7/0805 , H03L7/0814 , H03L7/10
摘要： A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.
摘要翻译：补偿过程，电压和温度变化的延迟线包括被配置为将数字信号延迟数字信号的时钟周期的延迟锁定环（DLL），该DLL包括布置为多个级联子串的DLL延迟线为了响应于数字控制信号，延迟每个子延迟线提供多个延迟量子中的一个。分馏电路被配置为产生作为数字控制信号的一部分的数字延迟线控制信号。数字延迟线被布置为多个级联子延迟线，每个子延迟线响应于数字延迟线控制信号提供多个延迟量子中的一个。

4. 发明授权

US07932744B1 Staggered I/O groups for integrated circuits 有权
标题翻译：用于集成电路的交错I / O组
公开(公告)号：US07932744B1
公开(公告)日：2011-04-26
申请号：US12142118
申请日：2008-06-19
申请人： Jonathan W. Greene , Gregory W. Bakker , Suhail Zain
发明人： Jonathan W. Greene , Gregory W. Bakker , Suhail Zain
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H01L24/06 , H01L2224/05554 , H01L2924/14 , H01L2924/00
摘要： An I/O scheme for an integrated circuit includes a group layout cell. The group layout cell includes a plurality of signal I/O pads. A driver circuit is coupled to each signal I/O pad. The group layout cell also includes two I/O driver-circuit power-supply pads. ESD protection circuitry is coupled to the plurality of driver circuits. The signal I/O pads and the I/O driver-circuit power-supply pads are arranged in rows. The rows may be regular or staggered.
摘要翻译：集成电路的I / O方案包括组布局单元。组布局单元包括多个信号I / O焊盘。驱动器电路耦合到每个信号I / O焊盘。组布局单元还包括两个I / O驱动器电路电源板。 ESD保护电路耦合到多个驱动器电路。信号I / O焊盘和I / O驱动器电路电源板排列成行。行可以是规则的或交错的。

5. 发明申请

US20060232296A1 Fast processing path using field programmable gate array logic unit 有权
标题翻译：使用现场可编程门阵列逻辑单元的快速处理路径
公开(公告)号：US20060232296A1
公开(公告)日：2006-10-19
申请号：US11108927
申请日：2005-04-18
申请人： Man Wang , Suhail Zain
发明人： Man Wang , Suhail Zain
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728 , H03K19/1774 , H03K19/17792
摘要： The described embodiments relate to the general area of Field Programmable Gate Arrays (FPGAs), and, in particular, to the architecture and the structure of the building blocks of the FPGAs. Proposed logic units, as separate units or a chain of units, which are mainly comprised of look-up tables, multiplexers, and latches, implement different mathematical and logical functions. Having two outputs, the embodiments of the logic unit can operate in a split mode and perform two separate logic and/or arithmetic functions at the same time. Chains of the proposed logic units, wherein every other unit is clocked by one of the two half clock cycles and utilizes local interconnections instead of traditional routing channels, add to efficiency and speed, and reduce required real estate.
摘要翻译：所描述的实施例涉及现场可编程门阵列（FPGA）的一般区域，尤其涉及FPGA的构建块的架构和结构。建议的逻辑单元，作为主要由查找表，多路复用器和锁存器组成的单独单元或单元链，实现不同的数学和逻辑功能。具有两个输出，逻辑单元的实施例可以以分割模式操作，并且同时执行两个单独的逻辑和/或算术功能。所提出的逻辑单元的链路，其中每隔一个单元由两个半个时钟周期中的一个计时，并利用局部互连而不是传统的路由信道，增加效率和速度，并减少所需的房地产。

6. 发明申请

US20140006730A1 MEMORY CONTROLLER DEVICES, SYSTEMS AND METHODS FOR HIGH RELIABILITY MEMORY DEVICES 有权
标题翻译：用于高可靠性存储器件的存储器控制器器件，系统和方法
公开(公告)号：US20140006730A1
公开(公告)日：2014-01-02
申请号：US13537877
申请日：2012-06-29
申请人： Suhail Zain , Helmut Puchner , Walt Anderson , Karthik Navalpakam
发明人： Suhail Zain , Helmut Puchner , Walt Anderson , Karthik Navalpakam
IPC分类号： G06F12/00
CPC分类号： G06F13/16 , G06F12/00 , G06F13/1668 , G06F13/1673 , G06F13/1694
摘要： A device can include a controller interface having at least one controller data output configured to output read data, and at least one controller data input configured to receive write data; and a memory device interface having a write data output configured to transmit the write data on rising and falling edges of a periodic signal, and a read data input configured to receive the read data at a same transmission rate as the write data.
摘要翻译：设备可以包括控制器接口，其具有被配置为输出读取数据的至少一个控制器数据输出，以及被配置为接收写入数据的至少一个控制器数据输入; 以及存储器件接口，其具有被配置为在周期信号的上升沿和下降沿发送写入数据的写入数据输出，以及被配置为以与写入数据相同的传输速率接收读取的数据的读取数据输入。

7. 发明授权

US07193436B2 Fast processing path using field programmable gate array logic units 有权
标题翻译：使用现场可编程门阵列逻辑单元的快速处理路径
公开(公告)号：US07193436B2
公开(公告)日：2007-03-20
申请号：US11108927
申请日：2005-04-18
申请人： Man Wang , Suhail Zain
发明人： Man Wang , Suhail Zain
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728 , H03K19/1774 , H03K19/17792
摘要： The described embodiments relate to the general area of Field Programmable Gate Arrays (FPGAs), and, in particular, to the architecture and the structure of the building blocks of the FPGAs. Proposed logic units, as separate units or a chain of units, which are mainly comprised of look-up tables, multiplexers, and latches, implement different mathematical and logical functions. Having two outputs, the embodiments of the logic unit can operate in a split mode and perform two separate logic and/or arithmetic functions at the same time. Chains of the proposed logic units, wherein every other unit is clocked by one of the two half clock cycles and utilizes local interconnections instead of traditional routing channels, add to efficiency and speed, and reduce required real estate.
摘要翻译：所描述的实施例涉及现场可编程门阵列（FPGA）的一般区域，尤其涉及FPGA的构建块的架构和结构。建议的逻辑单元，作为主要由查找表，多路复用器和锁存器组成的单独单元或单元链，实现不同的数学和逻辑功能。具有两个输出，逻辑单元的实施例可以以分割模式操作，并且同时执行两个单独的逻辑和/或算术功能。所提出的逻辑单元的链路，其中每隔一个单元由两个半个时钟周期中的一个计时，并利用局部互连而不是传统的路由信道，增加效率和速度，并减少所需的房地产。

8. 发明授权

US09304953B2 Memory controller devices, systems and methods for translating memory requests between first and second formats for high reliability memory devices 有权
标题翻译：存储器控制器设备，用于在第一和第二格式之间转换用于高可靠性存储器件的存储器请求的方法
公开(公告)号：US09304953B2
公开(公告)日：2016-04-05
申请号：US13537877
申请日：2012-06-29
申请人： Suhail Zain , Helmut Puchner , Walt Anderson , Karthik Navalpakam
发明人： Suhail Zain , Helmut Puchner , Walt Anderson , Karthik Navalpakam
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/16 , G06F12/00 , G06F13/1668 , G06F13/1673 , G06F13/1694
摘要： A device can include an interface circuit configured to translate memory access requests at a controller interface of the interface circuit into signals at a memory device interface of the interface circuit that is different from the controller interface, the interface circuit including a write buffer memory configured to store a predetermined number of data values received at a write input of the controller interface, and a read buffer memory configured to mirror a predetermined number of data values stored in the write buffer memory; wherein the memory device interface comprises an address output configured to transmit address values, a write data output configured to transmit write data on rising and falling edges of a periodic signal, and a read data input configured to receive read data at the same rate as the write data.
摘要翻译：一种设备可以包括接口电路，其被配置为将接口电路的控制器接口处的存储器访问请求转换为与控制器接口不同的接口电路的存储器设备接口处的信号，该接口电路包括写入缓冲存储器，存储在控制器接口的写入输入处接收到的预定数量的数据值;以及读缓冲存储器，被配置为镜像存储在写缓冲存储器中的预定数量的数据值; 其中所述存储器设备接口包括被配置为发送地址值的地址输出，被配置为在周期性信号的上升沿和下降沿发送写入数据的写入数据输出，以及被配置为以与所述周期性信号相同的速率接收读取数据的读取数据输入写数据

9. 发明授权

US08861271B1 High reliability non-volatile static random access memory devices, methods and systems 有权
标题翻译：高可靠性非易失性静态随机存取存储器件，方法与系统
公开(公告)号：US08861271B1
公开(公告)日：2014-10-14
申请号：US13536661
申请日：2012-06-28
申请人： Suhail Zain , Helmut Puchner , Walt Anderson , David Still
发明人： Suhail Zain , Helmut Puchner , Walt Anderson , David Still
IPC分类号： G11C16/04
CPC分类号： G11C11/41 , G06F17/5068 , G11C7/02 , G11C8/20 , G11C14/00 , G11C16/0441 , G11C16/10 , G11C16/22 , G11C16/26
摘要： A device can include a plurality of memory cells, each memory cell including at least one latch circuit coupled between two data nodes, a first nonvolatile section coupled to a first data node, and a second nonvolatile section coupled to a second data node; and each nonvolatile section including at least one switch element in series with a programmable nonvolatile element, the switch element configured to couple the nonvolatile element to the corresponding data node during a high reliability read operation of the memory cell.
摘要翻译：设备可以包括多个存储器单元，每个存储器单元包括耦合在两个数据节点之间的至少一个锁存电路，耦合到第一数据节点的第一非易失性部分和耦合到第二数据节点的第二非易失性部分; 并且每个非易失性部分包括与可编程非易失性元件串联的至少一个开关元件，所述开关元件被配置为在所述存储器单元的高可靠性读取操作期间将所述非易失性元件耦合到相应的数据节点。

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