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    • 5. 发明授权
    • System and method for assembling a data packet
    • 用于组装数据包的系统和方法
    • US07821931B2
    • 2010-10-26
    • US11924500
    • 2007-10-25
    • Erik R. SwensonChristopher J. Young
    • Erik R. SwensonChristopher J. Young
    • H04J1/16H04L12/26
    • H04L49/30H04L45/7453H04L45/7457
    • Disclosed is a system and method for assembling a data packet. The system can be implemented as four memory elements associated with one or more processors. The first memory element stores a sequence number and a sub-channel identifier for an incoming data packet. The second memory element stores a revised packet fragment. The third memory element stores an unrevised packet fragment. The fourth memory element stores a starting address. In the system, the starting address may be the starting address of the revised packet fragment or the unrevised packet fragment wherein the first memory element identifies portions of the fourth memory element associated with the sequence number. The one or more processors are configured to create a modified data packet by combining the unrevised packet fragments and the revised packet fragment, wherein the modified data packet is associated with the sequence number and sub-channel identifier.
    • 公开了一种用于组装数据分组的系统和方法。 该系统可以被实现为与一个或多个处理器相关联的四个存储器元件。 第一存储器元件存储用于输入数据分组的序列号和子信道标识符。 第二存储器元件存储经修改的分组片段。 第三存储器元件存储未修改的分组片段。 第四存储元件存储起始地址。 在系统中,起始地址可以是经修改的分组片段或未修改分组片段的起始地址,其中第一存储器元素标识与序列号相关联的第四存储器元件的部分。 一个或多个处理器被配置为通过组合未修改的分组片段和经修改的分组片段来创建修改的数据分组,其中修改的数据分组与序列号和子频道标识符相关联。
    • 6. 发明授权
    • System and method for egress packet marking
    • 出口分组标记的系统和方法
    • US07613209B1
    • 2009-11-03
    • US10814729
    • 2004-03-30
    • Kha H. NguyenErik R. Swenson
    • Kha H. NguyenErik R. Swenson
    • H04J3/24G06F15/16
    • H04L47/10H04L47/2408H04L47/2458H04L47/31H04L69/12H04L69/22H04L69/324H04L69/325
    • A packet processing system architecture and method are provided. According to one implementation, the system can include a first and second memory elements and a processor. The first memory element may be utilized for storing: A plurality of packet quality of service indicators; A first packet quality of service field; and A second packet quality of service field. The second memory element is utilized for storing a plurality of second packet quality of service indicators. The processor is operatively coupled to the memory elements for receiving quality of service commands, wherein the service commands include a plurality of third packet quality of service indicators. The processor uses an index to search the second memory element and the search returns a subset of the plurality of second packet quality of service indicators. The index may be the egress marking set or a queue number. The processor then creates a modified data packet by determining which of the packet quality of service fields to insert in the data packet, wherein the determination is based on the one or more quality of service commands.
    • 提供了一种分组处理系统架构和方法。 根据一个实现,系统可以包括第一和第二存储器元件和处理器。 第一存储器元件可以用于存储:多个服务质量指示符; 第一包服务质量领域; 和第二个分组服务质量领域。 第二存储器元件用于存储多个第二分组服务质量指示符。 处理器可操作地耦合到存储器元件,用于接收服务质量命令,其中服务命令包括多个第三分组服务质量指示符。 处理器使用索引来搜索第二存储器元件,并且搜索返回多个第二分组服务质量指示符的子集。 索引可以是出口标记集或队列号。 然后,处理器通过确定要插入到数据分组中的服务字段的分组质量来创建修改的数据分组,其中所述确定基于一个或多个服务质量命令。
    • 8. 发明授权
    • System and method for packet processor status monitoring
    • 分组处理器状态监控的系统和方法
    • US07539750B1
    • 2009-05-26
    • US10814728
    • 2004-03-30
    • David K. ParkerErik R. SwensonChristopher J. Young
    • David K. ParkerErik R. SwensonChristopher J. Young
    • G06F15/16G06F12/00
    • G06F15/16
    • Disclosed herein are a system and method for status monitoring, including debug error detection, during data packet processing. In general terms, the system for status monitoring during data packet processing can be implemented as a system including a packet processor and a buffer. The packet processor generates processing data based on one or more control structures while revising packet data. The packet processor generates the processing data while performing one or more lookup cycles. The buffer records the processing data and the status of the one or more control structures. The processing data includes a lookup number and the lookup number identifies the number of cycles performed by the packet processor.
    • 这里公开了一种用于状态监视的系统和方法,包括在数据分组处理期间的调试错误检测。 一般来说,数据分组处理期间的状态监视系统可以实现为包括分组处理器和缓冲器的系统。 分组处理器在修改分组数据的同时基于一个或多个控制结构生成处理数据。 分组处理器在执行一个或多个查找周期时产生处理数据。 缓冲器记录处理数据和一个或多个控制结构的状态。 处理数据包括查找号码,查找​​号码标识由分组处理器执行的周期数。