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1. 发明授权

US09106719B2 Real-time video optimizer 有权
标题翻译：实时视频优化器
公开(公告)号：US09106719B2
公开(公告)日：2015-08-11
申请号：US13448214
申请日：2012-04-16
申请人： Erik R. Swenson , Nitin Bhandari , Jaime Heilpern , Robert Oberhofer
发明人： Erik R. Swenson , Nitin Bhandari , Jaime Heilpern , Robert Oberhofer
IPC分类号： G06F15/16 , H04L29/06 , H04N21/2343 , H04N21/6379 , H04L29/08 , H04N19/156 , H04N19/40
CPC分类号： H04L65/60 , H04L65/1076 , H04L65/80 , H04L67/2823 , H04L67/303 , H04N19/156 , H04N19/40 , H04N21/234309 , H04N21/6379
摘要： A video optimizer receives a request to optimize a video, wherein the request includes optimization parameters and a uniform resource locator (URL) of the video. The video optimizer retrieves the video from an origin server and transcodes the video based on optimization parameters. The video optimizer load balances several transcoding sessions over one or more servers and tracks each session based on session identifications (IDs). Additionally, the video optimizer tracks each session to determine when a server is at or near capacity to prevent an overflow situation. The video optimizer is also enabled to stitch together two or more transcoding sessions in the event of a seek operation by a user during video playback. The video optimizer streams the video to the client device, enabling the client device to stream videos in substantially real-time after requesting the video.
摘要翻译：视频优化器接收优化视频的请求，其中请求包括视频的优化参数和统一资源定位符（URL）。视频优化器从原始服务器检索视频，并根据优化参数对视频进行转码。视频优化器通过一个或多个服务器负载平衡多个代码转换会话，并根据会话标识（ID）跟踪每个会话。此外，视频优化器跟踪每个会话以确定服务器何时处于或接近能力以防止溢出情况。视频优化器还可以在视频播放期间在用户进行搜索操作的情况下将两个或更多个代码转换会话拼接在一起。视频优化器将视频流传输到客户端设备，使客户端设备在请求视频后能够基本上实时流式传输视频。

2. 发明授权

US08392950B2 Architecture for delivery of video content responsive to remote interaction 有权
公开(公告)号：US08392950B2
公开(公告)日：2013-03-05
申请号：US11929773
申请日：2007-10-30
申请人： Erik R. Swenson , Nitin Bhandari , Michael Guzewicz , Nirmal Nair
发明人： Erik R. Swenson , Nitin Bhandari , Michael Guzewicz , Nirmal Nair
IPC分类号： H04N5/445
摘要： Systems and methods pertaining to a client-server architecture for communicating video frames across a network are disclosed. In one embodiment, a system includes a first engine residing on a first device, with the first engine adapted to encode a succession of video frames of a user interface of a program for transmission across the network. The encoding of the video frames is based on one or more feedback parameters and includes video compression techniques. In the same embodiment, the system includes a first command process engine operatively coupled to the program. In the same embodiment, the system includes a second engine residing on a second device, the second engine adapted to decode the succession of video frames after transmission across the network. In the same embodiment, the system includes a second command process engine operatively coupled to the first command process engine and adapted to communicate user input of the second device to the program via the first command process engine.

3. 发明申请

US20120265847A1 Real-Time Video Detector 有权
标题翻译：实时视频检测器
公开(公告)号：US20120265847A1
公开(公告)日：2012-10-18
申请号：US13448227
申请日：2012-04-16
申请人： Erik R. Swenson , Nitin Bhandari , Jaime Heilpern , Robert Oberhofer , John Hansen
发明人： Erik R. Swenson , Nitin Bhandari , Jaime Heilpern , Robert Oberhofer , John Hansen
IPC分类号： G06F15/16
CPC分类号： H04L65/60 , H04L65/1076 , H04L65/80 , H04L67/2823 , H04L67/303 , H04N19/156 , H04N19/40 , H04N21/234309 , H04N21/6379
摘要： A request to retrieve data from a client device is intercepted by a video detector. The video detector determines if the request is for retrieving a video file. If the request is for a video file, and the video file is deemed to be transcoded to be displayed on the client device, the video detector forwards the request to a video optimizer along with encoding parameters. Encoding parameters are selected by the video detector based on properties of the client device, networks accessible by the client device, conditions of those networks, properties of the requested video and the type of video requested. The encoding parameters also include a file format type to which the requested video is to be transcoded.
摘要翻译：从客户端设备检索数据的请求被视频检测器截取。视频检测器确定该请求是否用于检索视频文件。如果请求是用于视频文件，并且视频文件被认为被转码以在客户端设备上显示，则视频检测器将该请求与编码参数一起转发到视频优化器。编码参数由视频检测器根据客户端设备的属性，可由客户端设备访问的网络，这些网络的条件，请求的视频的属性以及所请求的视频的类型来选择。编码参数还包括要被转码到所请求的视频的文件格式类型。

4. 发明授权

US08161270B1 Packet data modification processor 有权
标题翻译：分组数据修改处理器
公开(公告)号：US08161270B1
公开(公告)日：2012-04-17
申请号：US10814556
申请日：2004-03-30
申请人： David K. Parker , Erik R. Swenson , Christopher J. Young
发明人： David K. Parker , Erik R. Swenson , Christopher J. Young
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3867 , G06F9/30018 , G06F9/30029 , G06F9/345 , H04L49/30
摘要： A programmable processor configured to perform one or more packet modifications through execution of one or more commands. A pipelined processor core comprises a first stage configured to selectively shift and mask data in each of a plurality of categories in response to one or more decoded commands, and combine the selectively shifted and masked data in each of the categories. The pipelined processor core further comprises a second stage configured to selectively perform one or more operations on the combined data from the first stage and other data responsive to the one or more decoded commands. In one implementation, the processor is implemented as an application specific integrated circuit (ASIC).
摘要翻译：配置为通过执行一个或多个命令来执行一个或多个分组修改的可编程处理器。流水线处理器核心包括第一级，其被配置为响应于一个或多个解码的命令来选择性地移位和屏蔽多个类别中的每一个中的数据，并且组合每个类别中的有选择地移位和屏蔽的数据。流水线处理器核心还包括第二级，其被配置为响应于一个或多个解码的命令，选择性地对来自第一级的组合数据和其他数据执行一个或多个操作。在一个实现中，处理器被实现为专用集成电路（ASIC）。

5. 发明授权

US07821931B2 System and method for assembling a data packet 有权
标题翻译：用于组装数据包的系统和方法
公开(公告)号：US07821931B2
公开(公告)日：2010-10-26
申请号：US11924500
申请日：2007-10-25
申请人： Erik R. Swenson , Christopher J. Young
发明人： Erik R. Swenson , Christopher J. Young
IPC分类号： H04J1/16 , H04L12/26
CPC分类号： H04L49/30 , H04L45/7453 , H04L45/7457
摘要： Disclosed is a system and method for assembling a data packet. The system can be implemented as four memory elements associated with one or more processors. The first memory element stores a sequence number and a sub-channel identifier for an incoming data packet. The second memory element stores a revised packet fragment. The third memory element stores an unrevised packet fragment. The fourth memory element stores a starting address. In the system, the starting address may be the starting address of the revised packet fragment or the unrevised packet fragment wherein the first memory element identifies portions of the fourth memory element associated with the sequence number. The one or more processors are configured to create a modified data packet by combining the unrevised packet fragments and the revised packet fragment, wherein the modified data packet is associated with the sequence number and sub-channel identifier.
摘要翻译：公开了一种用于组装数据分组的系统和方法。该系统可以被实现为与一个或多个处理器相关联的四个存储器元件。第一存储器元件存储用于输入数据分组的序列号和子信道标识符。第二存储器元件存储经修改的分组片段。第三存储器元件存储未修改的分组片段。第四存储元件存储起始地址。在系统中，起始地址可以是经修改的分组片段或未修改分组片段的起始地址，其中第一存储器元素标识与序列号相关联的第四存储器元件的部分。一个或多个处理器被配置为通过组合未修改的分组片段和经修改的分组片段来创建修改的数据分组，其中修改的数据分组与序列号和子频道标识符相关联。

6. 发明授权

US07613209B1 System and method for egress packet marking 有权
标题翻译：出口分组标记的系统和方法
公开(公告)号：US07613209B1
公开(公告)日：2009-11-03
申请号：US10814729
申请日：2004-03-30
申请人： Kha H. Nguyen , Erik R. Swenson
发明人： Kha H. Nguyen , Erik R. Swenson
IPC分类号： H04J3/24 , G06F15/16
CPC分类号： H04L47/10 , H04L47/2408 , H04L47/2458 , H04L47/31 , H04L69/12 , H04L69/22 , H04L69/324 , H04L69/325
摘要： A packet processing system architecture and method are provided. According to one implementation, the system can include a first and second memory elements and a processor. The first memory element may be utilized for storing: A plurality of packet quality of service indicators; A first packet quality of service field; and A second packet quality of service field. The second memory element is utilized for storing a plurality of second packet quality of service indicators. The processor is operatively coupled to the memory elements for receiving quality of service commands, wherein the service commands include a plurality of third packet quality of service indicators. The processor uses an index to search the second memory element and the search returns a subset of the plurality of second packet quality of service indicators. The index may be the egress marking set or a queue number. The processor then creates a modified data packet by determining which of the packet quality of service fields to insert in the data packet, wherein the determination is based on the one or more quality of service commands.
摘要翻译：提供了一种分组处理系统架构和方法。根据一个实现，系统可以包括第一和第二存储器元件和处理器。第一存储器元件可以用于存储：多个服务质量指示符; 第一包服务质量领域; 和第二个分组服务质量领域。第二存储器元件用于存储多个第二分组服务质量指示符。处理器可操作地耦合到存储器元件，用于接收服务质量命令，其中服务命令包括多个第三分组服务质量指示符。处理器使用索引来搜索第二存储器元件，并且搜索返回多个第二分组服务质量指示符的子集。索引可以是出口标记集或队列号。然后，处理器通过确定要插入到数据分组中的服务字段的分组质量来创建修改的数据分组，其中所述确定基于一个或多个服务质量命令。

7. 发明授权

US07546480B1 High speed bus with alignment, re-timing and buffer underflow/overflow detection enhancements 有权
标题翻译：具有对准，重新定时和缓冲下溢/溢出检测增强的高速总线
公开(公告)号：US07546480B1
公开(公告)日：2009-06-09
申请号：US11951672
申请日：2007-12-06
申请人： Erik R. Swenson , Sid Khattar
发明人： Erik R. Swenson , Sid Khattar
IPC分类号： G06F1/12 , G06F1/14
CPC分类号： G06F5/14
摘要： In a networked system in which high speed busses interconnect sources and destinations of data, systems for and methods of data alignment, data re-timing, and circular buffer underflow/overflow detection, are described. The invention is directed to a system for detecting either or both underflow and overflow of a circular buffer capable of holding n entries. The invention is also directed to a method of detecting either or both underflow and overflow of a circular buffer capable of holding n entries.
摘要翻译：在其中高速总线互连数据，数据对准系统和数据对准方法，数据重新定时和循环缓冲器下溢/溢出检测的网络系统中进行了描述。本发明涉及一种用于检测能够保存n个条目的循环缓冲器的下溢和上溢的系统。本发明还涉及一种检测能够保存n个条目的循环缓冲器的下溢和上溢的方法。

8. 发明授权

US07539750B1 System and method for packet processor status monitoring 有权
标题翻译：分组处理器状态监控的系统和方法
公开(公告)号：US07539750B1
公开(公告)日：2009-05-26
申请号：US10814728
申请日：2004-03-30
申请人： David K. Parker , Erik R. Swenson , Christopher J. Young
发明人： David K. Parker , Erik R. Swenson , Christopher J. Young
IPC分类号： G06F15/16 , G06F12/00
CPC分类号： G06F15/16
摘要： Disclosed herein are a system and method for status monitoring, including debug error detection, during data packet processing. In general terms, the system for status monitoring during data packet processing can be implemented as a system including a packet processor and a buffer. The packet processor generates processing data based on one or more control structures while revising packet data. The packet processor generates the processing data while performing one or more lookup cycles. The buffer records the processing data and the status of the one or more control structures. The processing data includes a lookup number and the lookup number identifies the number of cycles performed by the packet processor.
摘要翻译：这里公开了一种用于状态监视的系统和方法，包括在数据分组处理期间的调试错误检测。一般来说，数据分组处理期间的状态监视系统可以实现为包括分组处理器和缓冲器的系统。分组处理器在修改分组数据的同时基于一个或多个控制结构生成处理数据。分组处理器在执行一个或多个查找周期时产生处理数据。缓冲器记录处理数据和一个或多个控制结构的状态。处理数据包括查找号码，查找号码标识由分组处理器执行的周期数。

9. 发明申请

US20080184128A1 MOBILE DEVICE USER INTERFACE FOR REMOTE INTERACTION 审中-公开
标题翻译：用于远程互动的移动设备用户界面
公开(公告)号：US20080184128A1
公开(公告)日：2008-07-31
申请号：US12020472
申请日：2008-01-25
申请人： Erik R. Swenson , Nitin Bhandari , Alexander James Vincent , Dan Duong
发明人： Erik R. Swenson , Nitin Bhandari , Alexander James Vincent , Dan Duong
IPC分类号： G06F3/00 , G06F3/048
CPC分类号： H04N21/4782 , G09G5/14 , G09G2340/0407 , G09G2340/06 , G09G2340/145 , G09G2370/022 , G09G2370/042 , G09G2370/10 , H04N19/107 , H04N19/15 , H04N19/156 , H04N19/164 , H04N19/167 , H04N19/172 , H04N19/59 , H04N19/87 , H04N21/234336 , H04N21/41407 , H04N21/816 , H04N21/8451
摘要： Systems and methods pertaining to displaying a web browsing session are disclosed. In one embodiment, a system includes a web browsing engine residing on a first device, with a viewing application residing on a second device and operatively coupled to the web browsing engine, where the viewing application is adapted to display a portion of a webpage rendered by the web browsing engine and an overlay graphical component. In the same embodiment, the system also includes a recognition engine adapted to identify an element on the webpage and communicate information regarding the element to the viewing application.
摘要翻译：公开了显示网页浏览会话的系统和方法。在一个实施例中，系统包括驻留在第一设备上的网页浏览引擎，其中观看应用程序驻留在第二设备上并且可操作地耦合到网页浏览引擎，其中观看应用程序适于显示网页呈现的网页的一部分，网页浏览引擎和覆盖图形组件。在同一实施例中，该系统还包括适于识别网页上的元素并将关于元素的信息传达给观看应用的识别引擎。

10. 发明授权

US07130308B2 Data path architecture for a LAN switch 有权
标题翻译： LAN交换机的数据路径体系结构
公开(公告)号：US07130308B2
公开(公告)日：2006-10-31
申请号：US09952274
申请日：2001-09-13
申请人： Stephen R. Haddock , Justin N. Chueh , David K. Parker , Herb Schneider , R. Steven Smith , Erik R. Swenson
发明人： Stephen R. Haddock , Justin N. Chueh , David K. Parker , Herb Schneider , R. Steven Smith , Erik R. Swenson
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L47/2441 , H04L45/745 , H04L47/2416 , H04L47/50 , H04L47/6215 , H04L47/627 , H04L49/3018 , H04L49/351 , H04L49/352 , H04L49/354
摘要： A packet switching device having a central shared memory and a number of medium access controllers each coupled to a communications medium to exchange data packets, and a controller coupled to each medium access controller via a data path to exchange data packets with the media access controller. The controller has a number of data path controllers each connected to each medium access controller to exchange a corresponding portion of the data packets with the medium access controller. The data path controllers each have a number of buffers to hold the portion of the data packets exchanged with the corresponding medium access controller. Each data path controller has a selector that selects the buffer from which to exchange the portion of the data packets with the central shared memory and control logic that controls the selector to concurrently select the buffer corresponding to the same medium access controller.
摘要翻译：具有中央共享存储器和多个介质访问控制器的分组交换设备，每个媒体接入控制器都耦合到通信介质以交换数据分组;以及控制器，其经由数据路径耦合到每个介质访问控制器，以与介质访问控制器交换数据分组。控制器具有多个数据路径控制器，每个数据路径控制器连接到每个介质访问控制器，以将介质访问控制器的数据分组的相应部分交换。数据路径控制器各自具有多个缓冲器以保持与相应的介质访问控制器交换的数据分组的部分。每个数据路径控制器具有选择器，该选择器选择用于与中央共享存储器交换数据分组的一部分的缓冲器以及控制选择器同时选择对应于相同介质访问控制器的缓冲器的控制逻辑。

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