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1. 发明申请

US20120146727A1 FAST POWER UP COMPARATOR 失效
标题翻译：快速上电比较器
公开(公告)号：US20120146727A1
公开(公告)日：2012-06-14
申请号：US13323654
申请日：2011-12-12
申请人： Sasan Cyrusian
发明人： Sasan Cyrusian
IPC分类号： H03F3/45 , H03G3/20
CPC分类号： G06F1/3287 , G06F1/3234 , H03F1/0266 , H03F1/0272 , H03F1/0283 , H03F3/185 , H03F3/2173 , H03F3/2178 , H03F3/3022 , H03F3/3033 , H03F3/45183 , H03F3/4521 , H03F3/45475 , H03F3/72 , H03F2200/03 , H03F2200/264 , H03F2200/27 , H03F2200/321 , H03F2200/75 , H03F2200/78 , H03F2203/45466 , H03F2203/45471 , H03F2203/45504 , H03F2203/45506 , H03F2203/45512 , H03F2203/45674 , H03F2203/45726 , H03F2203/7203
摘要： A circuit method includes periodically increasing a tail current of a differential stage of a comparator to periodically power on the differential stage to a power-on state, and periodically decreasing the tail current of the differential stage to periodically power down the differential stage to a low-power state. The periodically increasing of the tail current and the periodically decreasing of the tail current are asynchronous operations for powering on the differential stage to the power-on state and powering down the differential stage to the low-power state. Periodically increasing the tail current and the periodically decreasing the tail current asynchronously for powering on the differential stage to the power-on state and powering down the differential stage to the low-power state provide for low noise and high speed during signal comparison.
摘要翻译：一种电路方法包括周期性地增加比较器的差分级的尾电流，以将差分级周期性地上电到上电状态，并且周期性地减小差分级的尾电流以周期性地将差分级降低到低电力状态。尾电流的周期性增加和尾电流的周期性减小是用于将差动级上电到上电状态的异步操作，并将差动级下电到低功率状态。周期性地增加尾电流和周期性地不同步地减小尾电流以使差动级上电到上电状态，并将差分级上电到低功率状态，在信号比较期间提供低噪声和高速度。

2. 发明申请

US20120139766A1 Digital to Analog Converter Circuits and Methods 失效
标题翻译：数模转换器电路和方法
公开(公告)号：US20120139766A1
公开(公告)日：2012-06-07
申请号：US13313455
申请日：2011-12-07
申请人： Sasan Cyrusian
发明人： Sasan Cyrusian
IPC分类号： H03M1/10 , H03M1/66
CPC分类号： H03M1/0845 , H03M1/00 , H03M1/0682 , H03M1/12 , H03M1/742 , H03M1/747 , H04B3/54 , H04L25/067 , H04L27/2647
摘要： The present disclosure provides for improved DAC circuits and methods. In one embodiment, a digital-to-analog converter receives a digital signal and outputs a first analog output signal corresponding to the digital signal. A current buffer receives the first analog output signal and generates an analog output current. The current output digital-to-analog converter and the current buffer are constructed on an integrated circuit, and the analog output current is coupled to a pin of the integrated circuit. The pin of the integrated circuit receives the analog output current and provides the analog output current to additional circuitry external to the integrated circuit.
摘要翻译：本公开提供了改进的DAC电路和方法。在一个实施例中，数模转换器接收数字信号并输出对应于数字信号的第一模拟输出信号。当前缓冲器接收第一模拟输出信号并产生模拟输出电流。电流输出数模转换器和当前缓冲器构成在集成电路上，模拟输出电流耦合到集成电路的引脚。集成电路的引脚接收模拟输出电流，并将模拟输出电流提供给集成电路外部的附加电路。

3. 发明授权

US06662303B1 Write precompensation circuit and read channel with write precompensation circuit that generates output signals by interpolating between selected phases 有权
标题翻译：通过写入预补偿电路来写入预补偿电路和读通道，可通过在所选相之间插值来产生输出信号
公开(公告)号：US06662303B1
公开(公告)日：2003-12-09
申请号：US09480875
申请日：2000-01-10
申请人： Zabih Toosky , Sasan Cyrusian , Ulrich Huewels
发明人： Zabih Toosky , Sasan Cyrusian , Ulrich Huewels
IPC分类号： G06F112
CPC分类号： G11B20/10009 , G11B5/09
摘要： An improved write precompensation circuit. Eight phases from a PLL phase oscillator are received as inputs into a bank of four phase blenders (104). The phase blenders (104) output a 0%, 25%, 50%, or 75% interpolation to the adjacent phases. A multiplexer (110) is then used to select which of the phase outputs is used for the write precompensation.
摘要翻译：一种改进的预预补偿电路。接收来自PLL相位振荡器的八个相位作为四相混合器（104）的一组输入。相位调节器（104）向相邻相输出0％，25％，50％或75％的内插。然后，多路复用器（110）用于选择哪个相位输出用于写入预补偿。

4. 发明授权

US06552865B2 Diagnostic system for a read/write channel in a disk drive 有权
标题翻译：磁盘驱动器中读/写通道的诊断系统
公开(公告)号：US06552865B2
公开(公告)日：2003-04-22
申请号：US09865651
申请日：2001-05-25
申请人： Sasan Cyrusian
发明人： Sasan Cyrusian
IPC分类号： G11B2736
CPC分类号： G11B27/36 , G11B5/012 , G11B20/10009 , G11B2220/20
摘要： The invention provides a read/write channel with a diagnostic system for a disk drive. The diagnostic system may process internal and external signals. The read/write channel may have one or more clock generators, a digital to analog converter, an analog comparator, and a successive approximation register. The read/write channel may be implemented on an integrated circuit or a complementary metal oxide semiconductor. The read/write channel may have partial response maximum likelihood (PRML) encoding and decoding. The diagnostic system uses bit-weighing or successive approximation to convert analog signals into digital diagnostic signals.
摘要翻译：本发明提供了一种具有用于磁盘驱动器的诊断系统的读/写通道。诊断系统可以处理内部和外部信号。读/写通道可以具有一个或多个时钟发生器，数模转换器，模拟比较器和逐次逼近寄存器。读/写通道可以在集成电路或互补金属氧化物半导体上实现。读/写通道可能具有部分响应最大似然（PRML）编码和解码。诊断系统使用位加权或逐次逼近将模拟信号转换为数字诊断信号。

5. 发明授权

US06552593B2 Active auto zero circuit for programmable time continuous open loop amplifiers 有权
公开(公告)号：US06552593B2
公开(公告)日：2003-04-22
申请号：US09896279
申请日：2001-06-29
申请人： Thomas Blon , Sasan Cyrusian
发明人： Thomas Blon , Sasan Cyrusian
IPC分类号： H03L500
CPC分类号： H03F3/45197 , H03F3/45659 , H03F3/45753 , H03F2203/45418 , H03F2203/45424 , H03F2203/45431 , H03F2203/45616 , H03F2203/45658
摘要： An active offset cancellation circuit for an open loop differential amplifier having programmable gain is disclosed. The amplifier is operated on a two-phase clock where the normal operation occurs on the first phase and offset detection and cancellation occurs on the second phase. On the first phase, the programmable gain of the amplifier is set according to the application of the amplifier. On the second phase, the programmable gain of the amplifier is set to the maximum value and the offset cancellation circuit measures the offset created by the amplifier when both differential inputs are connected to a common source. The circuit then adjusts a bias current and stores this adjustment to cancel offset during the operational phase of the amplifier. During the operational phase, the first phase of the clock, the programmable gain is again returned to a value according to the application and the stored adjustment is used to bias the current in one of the two input stages of the amplifier, canceling any offset imparted by the amplifier circuitry. One each clock cycle, any additional offset is similarly detected and canceled. Further, by varying the gain as described, residual offset is reduced.

6. 发明授权

US07492219B1 Power efficient amplifier 有权
标题翻译：功率放大器
公开(公告)号：US07492219B1
公开(公告)日：2009-02-17
申请号：US11786886
申请日：2007-04-12
申请人： Sasan Cyrusian
发明人： Sasan Cyrusian
IPC分类号： H03F3/38
CPC分类号： H03F3/217
摘要： An amplifier generates a tri-level output signal in response to an input signal that is pulse-width modulated. The amplifier is filterless and DC free. The amplifier includes an integrator, a signal generator, comparator, a switch pulse logic block, a driver, and a control block. The control block supplies a multitude of pulse-width modulated (PWM) signals in response to the received digital input signal. A pair of the PWM signals are applied to the signal generator which in response supplies a signal to the integrator. The integrator's output signal is compared to a reference signal by the comparator. The switch pulse logic block receives the output of the comparator and a pair of delayed PWM signals and in response generates a multitude of driver signals applied to the driver. The driver supplies an output signal that is adapted to vary between first, second and third voltages.
摘要翻译：放大器响应于脉冲宽度调制的输入信号产生三电平输出信号。放大器无滤波，无直流。放大器包括积分器，信号发生器，比较器，开关脉冲逻辑块，驱动器和控制块。控制块响应于接收到的数字输入信号提供多个脉冲宽度调制（PWM）信号。一对PWM信号被施加到信号发生器，信号发生器响应于向积分器提供信号。积分器的输出信号通过比较器与参考信号进行比较。开关脉冲逻辑块接收比较器的输出和一对延迟的PWM信号，并且响应于产生施加到驱动器的大量驱动信号。驱动器提供适于在第一，第二和第三电压之间变化的输出信号。

7. 发明授权

US06737919B2 Method and apparatus for calibrating a Gm cell utilizing a replica Gm cell 有权
标题翻译：使用复制Gm单元校准Gm单元的方法和装置
公开(公告)号：US06737919B2
公开(公告)日：2004-05-18
申请号：US09865649
申请日：2001-05-25
申请人： Sasan Cyrusian
发明人： Sasan Cyrusian
IPC分类号： H03F345
CPC分类号： H03M1/1014 , H03G1/0029
摘要： A method and apparatus for calibrating a Gm cell using a Gm replica cell. A digital to analog converter receives a Gm setting code and generates a reference current. The Gm replica cell adjusts the tuning voltage until the difference between a pair of drain currents is substantially equal to the reference current. Where this condition is satisfied, the proper tuning voltage has been acquired. This results in proper calibration for the tuning voltage, which then may be utilized by a Gm cell connected with the Gm replica cell.
摘要翻译：一种使用Gm复制单元校准Gm单元的方法和装置。数模转换器接收Gm设定码并产生参考电流。 Gm复制单元调节调谐电压，直到一对漏极电流之间的差异基本上等于参考电流。在满足该条件的情况下，已经获得适当的调谐电压。这导致对调谐电压的适当校准，其然后可以由与Gm复制单元连接的Gm单元利用。

8. 发明授权

US06570447B2 Programmable logarithmic gain adjustment for open-loop amplifiers 有权
公开(公告)号：US06570447B2
公开(公告)日：2003-05-27
申请号：US09866147
申请日：2001-05-25
申请人： Sasan Cyrusian , Thomas Blon
发明人： Sasan Cyrusian , Thomas Blon
IPC分类号： H03F345
CPC分类号： H03F3/45197 , H03G1/0088 , H03G7/00
摘要： Transconductance-based variable gain amplifiers amplify an input voltage by converting the voltage difference to a current and then amplifying the result. At least one resistor network is adjusted depending on the magnitude of the input voltage difference and the output desired. A network of MOS transistor switches with a small footprint adjusts the resistance of the input voltage circuit in a way to insure consistent resistance and low stray capacitance.

9. 发明授权

US06519103B2 View DAC feedback inside analog front circuit 有权
标题翻译：在模拟前置电路内查看DAC反馈
公开(公告)号：US06519103B2
公开(公告)日：2003-02-11
申请号：US09865757
申请日：2001-05-25
申请人： Sasan Cyrusian
发明人： Sasan Cyrusian
IPC分类号： G11B509
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/1816
摘要： A view DAC feedback inside an analog front circuit for a partial response, maximum likelihood based read/write channel is disclosed. The view DAC feedback circuit may be configured to apply an analog signal associated with an operation level of the PRML based read/write channel to the analog front circuit of the read channel. The view DAC analog signal may be used to calibrate operating parameters for a continuous time filter component of the analog front circuit. The view DAC feedback circuit may be configured to add digitally-controlled noise to the PRMIL read/write channel to optimize performance of the channel in a low signal-to-noise (SNR) environment.
摘要翻译：公开了用于部分响应的模拟前端电路中的视图DAC反馈，基于最大似然的读/写通道。视图DAC反馈电路可以被配置为将与基于PRML的读/写通道的操作电平相关联的模拟信号施加到读通道的模拟前端电路。视图DAC模拟信号可用于校准模拟前置电路的连续时间滤波器组件的工作参数。视图DAC反馈电路可以被配置为向PRMIL读/写通道添加数字控制的噪声，以在低信噪比（SNR）环境中优化信道的性能。

10. 发明授权

US06480128B1 High-speed sample-and-hold circuit with gain 有权
标题翻译：具有增益的高速采样保持电路
公开(公告)号：US06480128B1
公开(公告)日：2002-11-12
申请号：US09866378
申请日：2001-05-25
申请人： Elmar Bach , Sasan Cyrusian
发明人： Elmar Bach , Sasan Cyrusian
IPC分类号： H03M112
CPC分类号： G11C27/026 , G11C27/02 , H03M1/1245
摘要： A sample-and-hold system that includes a first source follower having an input and an output and a second source follower that includes an input connected in series with the output of the first source follower and that furthermore comprises of a sample-and-hold switch connected to an output of the second source follower.
摘要翻译：一种采样和保持系统，其包括具有输入和输出的第一源极跟随器和包括与第一源极跟随器的输出串联连接的输入的第二源极跟随器，并且还包括采样保持器开关连接到第二源极跟随器的输出端。

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