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1. 发明授权

US5313100A Multilayer interconnection structure for a semiconductor device 失效
标题翻译：半导体器件的多层互连结构
公开(公告)号：US5313100A
公开(公告)日：1994-05-17
申请号：US871228
申请日：1992-04-20
申请人： Atsushi Ishii , Yoshifumi Takata , Akihiko Ohsaki , Kazuyoshi Maekawa
发明人： Atsushi Ishii , Yoshifumi Takata , Akihiko Ohsaki , Kazuyoshi Maekawa
IPC分类号： H01L23/522 , H01L21/768 , H01L23/532 , H01L29/400 , H01L29/460
CPC分类号： H01L23/53223 , H01L2924/0002 , Y10S257/915
摘要： An aluminum interconnection film has a three layered structure of an aluminum alloy film, a tungsten film, and a titanium nitride film. An aluminum interconnection film and an aluminum interconnection film are electrically connected through a through hole formed in a silicon oxide film. Because light reflectivity of the titanium nitride film is low, the exposed area of the resist can be kept within a predetermined area even if photolithography is carried out above a step where light is irregularly reflected. Therefore, it is possible to form a through hole of a desired dimension even if the through hole is formed above the step. Even if the titanium nitride film is etched and removed in forming the through hole, the aluminum alloy film is not exposed since the etching speed of the silicon oxide film is considerably slower than that of the tungsten film. The problem of denatured layer formation and residue formation caused by exposure of aluminum alloy film does not occur.
摘要翻译：铝互连膜具有铝合金膜，钨膜和氮化钛膜的三层结构。铝互连膜和铝互连膜通过形成在氧化硅膜中的通孔电连接。由于氮化钛膜的光反射率低，所以即使在光不规则地反射的步骤上进行光刻，也可以将抗蚀剂的露出面积保持在规定的面积内。因此，即使在台阶上方形成通孔，也可以形成所需尺寸的通孔。即使在形成通孔时蚀刻和去除氮化钛膜，由于氧化硅膜的蚀刻速度比钨膜的蚀刻速度慢得多，因此铝合金膜不暴露。不会发生由铝合金膜暴露引起的变性层形成和残留物形成的问题。

2. 发明授权

US6147402A Refractory metal capped low resistivity metal conductor lines and vias 失效
$Refractory metal capped low resistivity metal conductor lines and vias$
标题翻译：耐火金属封盖的低电阻金属导线和通孔
公开(公告)号：US6147402A
公开(公告)日：2000-11-14
申请号：US113918
申请日：1998-07-10
申请人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
发明人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
IPC分类号： H01L21/28 , H01L21/312 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/498 , H01L23/522 , H01L23/532 , H01L29/440 , H01L29/460
CPC分类号： H01L21/76843 , H01L21/76838 , H01L21/7684 , H01L21/76847 , H01L21/76849 , H01L21/76852 , H01L21/76877 , H01L23/49866 , H01L23/53223 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/09701 , Y10S148/015 , Y10S257/915 , Y10S438/959
摘要： Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH.sub.4 to WF.sub.6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1 mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.
摘要翻译：用难熔金属覆盖低电阻率金属导体线或通孔允许有效地使用化学机械抛光技术，因为在化学机械抛光期间难熔金属的硬度降低的磨损特性不会划伤，腐蚀或涂抹。使用低电阻率金属或合金的物理气相沉积（例如，蒸发或准直溅射）以及随后的难熔金属的化学气相沉积（CVD）和随后的平坦化的组合来产生优异的导电线和通孔。在通过CVD施加难熔金属帽时改变SiH4与WF6的比率允许将钨控制并入钨覆盖层中。准直溅射允许在电介质中的开口中形成难熔金属衬垫，其适合作为铜基金属化的扩散阻挡层以及CVD钨。理想地，为了更快地扩散金属如铜，通过两步准直溅射工艺产生衬垫，其中第一层在相对低的真空压力下沉积，其中定向沉积占主导地位（例如，低于1mTorr），并且第二层沉积在较高的散射沉积占主导地位的真空压力（例如高于1mTorr）。对于诸如CVD钨的难熔金属，可以在较高的真空压力下使用准直溅射在一个步骤中创建衬垫。

3. 发明授权

US5442235A Semiconductor device having an improved metal interconnect structure 失效
标题翻译：具有改进的金属互连结构的半导体器件
公开(公告)号：US5442235A
公开(公告)日：1995-08-15
申请号：US172320
申请日：1993-12-23
申请人： Louis C. Parrillo , Jeffrey L. Klein
发明人： Louis C. Parrillo , Jeffrey L. Klein
IPC分类号： H01L23/522 , H01L23/532 , H01L29/460
CPC分类号： H01L23/53238 , H01L23/5226 , H01L23/53219 , H01L2924/0002 , Y10S438/927
摘要： A metal interconnect structure includes copper interface layers (24, 30) located between a refractory metal via plug (28), and first and second metal interconnect layers (16, 32). The copper interface layers (24, 30) are confined to the area of a via opening (22) in an insulating layer (20) overlying the first interconnect layer (16) and containing the via plug (28). The interface layers (24, 30) are subjected to an anneal to provide copper reservoirs (36, 37) in the interconnect layers (16, 32) adjacent to the interface layers (24, 30). The copper reservoirs (36, 37) continuously replenish copper depleted from the interface when an electric current is passed through the interconnect structure. A process includes the selective deposition of copper onto an exposed region (23) of the first metal interconnect layer (16), and onto the upper portion the via plug (28), followed by an anneal in forming gas to form the copper reservoirs (36, 37).
摘要翻译：金属互连结构包括位于耐火金属通孔塞（28）和第一和第二金属互连层（16,32）之间的铜界面层（24,30）。铜界面层（24,30）被限制在覆盖在第一互连层（16）上并包含通孔塞（28）的绝缘层（20）中的通路孔（22）的区域中。对界面层（24,30）进行退火处理，以在与界面层（24,30）相邻的互连层（16,32）中提供铜储存器（36,37）。当电流通过互连结构时，铜储存器（36,37）连续补充从界面耗尽的铜。一种方法包括将铜选择性沉积在第一金属互连层（16）的暴露区域（23）上，并在上部通孔塞（28）上，然后在形成气体中进行退火以形成铜储存器 36,37）。

4. 发明授权

US5300813A Refractory metal capped low resistivity metal conductor lines and vias 失效
$Refractory metal capped low resistivity metal conductor lines and vias$
标题翻译：耐火金属封盖的低电阻金属导线和通孔
公开(公告)号：US5300813A
公开(公告)日：1994-04-05
申请号：US841967
申请日：1992-02-26
申请人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
发明人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
IPC分类号： H01L21/28 , H01L21/312 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/498 , H01L23/522 , H01L23/532 , H01L29/440 , H01L29/460
CPC分类号： H01L21/76843 , H01L21/76838 , H01L21/7684 , H01L21/76847 , H01L21/76849 , H01L21/76852 , H01L21/76877 , H01L23/49866 , H01L23/53223 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/09701 , Y10S148/015 , Y10S257/915 , Y10S438/959
摘要： A contact structure for a semiconductor device having a first refractory metal layer formed only at the bottom of a contact hole. The first refractory metal is selected from a group comprising titanium (Ti), titanium alloys or compounds such as Ti/TiN, tungsten (W), titanium/tungsten (Ti/W) alloys, or chromium (Cr) or tantalum (Ta) and their alloys or some other suitable material. A low resistivity layer comprising a single, binary or ternary metalization is deposited over the first refractory metal layer in the contact hole by a method such as PVD using evaporation or collimated sputtering. The low resistivity layer has side walls which taper inwardly toward one another with increasing height of the layer and the low resistivity layer does not contact the side walls of the contact hole. The low resistivity layer may be Al.sub.x Cu.sub.y (x+y=1; x.gtoreq.0, y.gtoreq.0), ternary alloys such as Al-Pd-Cu or multicomponent alloys such as Al-Pd-Nb-Au. A second refractory metal layer is deposited over the low resistivity layer. The second refractory metal layer may be tungsten, cobalt, nickel, molybdenum or alloys/compounds such as Ti/TiN. The first and second refractory metal layers completely encapsulate the low resistivity layer. The first and second refractory metal layers can comprise an alloy containing silicon with a higher incorporated silicon content near the top of the contact hold present as a distinct or graded composition than at a location closer to the bottom of the contact hole.
摘要翻译：一种用于半导体器件的接触结构，其具有仅在接触孔的底部形成的第一难熔金属层。第一难熔金属选自钛（Ti），钛合金或Ti / TiN，钨（W），钛/钨（Ti / W）合金或铬（Cr）或钽（Ta）及其合金或其他合适的材料。包含单一二元或三元金属化的低电阻率层通过诸如使用蒸发或准直溅射的PVD的方法沉积在接触孔中的第一难熔金属层上。低电阻率层具有随着层的高度逐渐向内逐渐向内逐渐变细的侧壁，低电阻层不接触接触孔的侧壁。低电阻率层可以是AlxCuy（x + y = 1; x> = 0，y> = 0），诸如Al-Pd-Cu的三元合金或诸如Al-Pd-Nb-Au的多组分合金。在低电阻率层上沉积第二难熔金属层。第二耐火金属层可以是钨，钴，镍，钼或诸如Ti / TiN的合金/化合物。第一和第二难熔金属层完全封装低电阻率层。第一和第二难熔金属层可以包含含有硅的合金，其中接合保持层的顶部附近具有更高的掺入硅含量，作为不同或分级的组成，而不是靠近接触孔底部的位置。

5. 发明授权

US5331198A Semiconductor device including IIL and vertical transistors 失效
标题翻译：包括IIL和垂直晶体管的半导体器件
公开(公告)号：US5331198A
公开(公告)日：1994-07-19
申请号：US924986
申请日：1992-08-05
申请人： Akihiro Kanda , Mitsuo Tanaka , Takehiro Hirai , Masahiro Nakatani
发明人： Akihiro Kanda , Mitsuo Tanaka , Takehiro Hirai , Masahiro Nakatani
IPC分类号： H01L21/74 , H01L21/8226 , H01L21/8228 , H01L27/082 , H01L29/730 , H01L29/120 , H01L29/460
CPC分类号： H01L21/82285 , H01L21/743 , H01L21/8226 , H01L27/0826 , Y10S148/087
摘要： The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1) . The IIL comprises an emitter, a base and a collector which are respectively comprised of a high-density n.sup.+ -type first buried layer (5), a p.sup.+ -type second buried layer (8) having a lower impurity density than the n.sup.+ -type first buried layer (5), and at least one of n.sup.+ -type diffused layer (31). The semiconductor device thus constituted makes it possible to increase the emitter injection efficiency while the base impurity density is kept high, and also to decrease the base width, so that the collector-emitter breakdown voltage and current gain of the IIL can be more improved and also the operation speed of the IIL can be made higher.
摘要翻译：本发明提供一种半导体器件，特别是包括集成在同一导电型半导体衬底（1）上的垂直npn晶体管，垂直pnp晶体管和IIL的半导体器件。 IIL包括发射极，基极和集电极，它们分别由高密度n +型第一掩埋层（5），具有比n +型杂质密度低的杂质密度的p +型第二掩埋层（8）第一掩埋层（5）和n +型扩散层（31）中的至少一个。这样构成的半导体装置能够提高发射极注入效率，同时保持基极杂质浓度高，并且还可以降低基极宽度，从而可以进一步提高IIL的集电极 - 发射极击穿电压和电流增益，也可以使IIL的运行速度更高。

6. 发明授权

US5293071A Bump structure for bonding to a semi-conductor device 失效
标题翻译：用于结合到半导体器件的凹凸结构
公开(公告)号：US5293071A
公开(公告)日：1994-03-08
申请号：US836580
申请日：1992-02-18
申请人： George Erdos
发明人： George Erdos
IPC分类号： H01L21/60 , H01L21/603 , H01L23/485 , H01L29/440 , H01L29/460
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/11 , H01L2224/1147 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01056 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/14
摘要： A bump structure for bonding leads to a semi-conductor, in which the bump has a thin lower portion which overlaps and seals the edges of the passivation layer, and a thicker upper or stem portion of smaller lateral dimensions to fit within the margins of the opening in the passivation layer. Thus, during bonding, downward compressive forces are applied primarily through the bump stem directly to the metal termination pad beneath the bump, and very little force is applied to the edges of the passivation layer. This reduces the likelihood of passivation layer cracking, increasing device reliability. Because the bump stem is formed within the margins of the passivation layer opening, it has a flat top, resulting in better lead bonding.
摘要翻译：用于接合的凸起结构引导到半导体，其中凸块具有与钝化层的边缘重叠并密封的较薄的下部，以及更小的侧向尺寸的更厚的上部或主要部分以适合在该半导体的边缘内在钝化层中开口。因此，在接合期间，向下的压缩力主要通过凸块直接施加到凸块下方的金属端接垫，并且很少的力施加到钝化层的边缘。这降低了钝化层破裂的可能性，增加了器件的可靠性。由于凸起柄形成在钝化层开口的边缘内，所以其具有平坦的顶部，导致更好的引线键合。

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