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1. 发明授权

US5712140A Method of manufacturing interconnection structure of a semiconductor device 失效
标题翻译：制造半导体器件的互连结构的方法
公开(公告)号：US5712140A
公开(公告)日：1998-01-27
申请号：US816201
申请日：1997-03-25
申请人： Atsushi Ishii , Yoshifumi Takata , Akihiko Ohsaki , Kazuyoshi Maekawa
发明人： Atsushi Ishii , Yoshifumi Takata , Akihiko Ohsaki , Kazuyoshi Maekawa
IPC分类号： H01L23/522 , H01L21/768 , H01L23/532 , H01L21/283
CPC分类号： H01L23/53223 , H01L2924/0002 , Y10S257/915
摘要： An aluminum interconnection film has a three layered structure of an aluminum alloy film, a tungsten film, and a titanium nitride film. An aluminum interconnection film and a second aluminum interconnection film are electrically connected through a through hole formed in a silicon oxide film. Because light reflectivity of the titanium nitride film is low, the exposed area of the resist can be kept within a predetermined area even if photolithography is carried out above a step where light is irregularly reflected. Therefore, it is possible to form a through hole of a desired dimension even if the through hole is formed above the step. Even if the titanium nitride film is etched and removed in forming the through hole, the aluminum alloy film is not exposed since the etching speed of the silicon oxide film is considerably slower than that of the tungsten film. The problem of denatured layer formation and residue formation caused by exposure of aluminum alloy film does not occur.
摘要翻译：铝互连膜具有铝合金膜，钨膜和氮化钛膜的三层结构。铝互连膜和第二铝互连膜通过形成在氧化硅膜中的通孔电连接。由于氮化钛膜的光反射率低，所以即使在光不规则地反射的步骤上进行光刻，也可以将抗蚀剂的露出面积保持在规定的面积内。因此，即使在台阶上方形成通孔，也可以形成所需尺寸的通孔。即使在形成通孔时蚀刻和去除氮化钛膜，由于氧化硅膜的蚀刻速度比钨膜的蚀刻速度慢得多，因此铝合金膜不暴露。不会发生由铝合金膜暴露引起的变性层形成和残留物形成的问题。

2. 发明授权

US5475267A Multilayer interconnection structure for a semiconductor device 失效
标题翻译：半导体器件的多层互连结构
公开(公告)号：US5475267A
公开(公告)日：1995-12-12
申请号：US354737
申请日：1994-12-08
申请人： Atsushi Ishii , Yoshifumi Takata , Akihiko Ohsaki , Kazuyoshi Maekawa
发明人： Atsushi Ishii , Yoshifumi Takata , Akihiko Ohsaki , Kazuyoshi Maekawa
IPC分类号： H01L23/522 , H01L21/768 , H01L23/532 , H01L29/43
CPC分类号： H01L23/53223 , H01L2924/0002 , Y10S257/915
摘要： An aluminum interconnection film has a three layered structure of an aluminum alloy film, a tungsten film, and a titanium nitride film. An aluminum interconnection film and an aluminum interconnection film are electrically connected through a through hole formed in a silicon oxide film, one embodiment using a tungsten plug for the electrical connection. Because light reflectivity of the titanium nitride film is low, the exposed area of the resist can be kept within a predetermined area even if photolithography is carried out above a step where light is irregularly reflected. Therefore, it is possible to form a through hole of a desired dimension even if the through hole is formed above the step. Even if the titanium nitride film is etched and removed in forming the through hole, the aluminum alloy film is not exposed since the etching speed of the silicon oxide film is considerably slower than that of the tungsten film. The problem of denatured layer formation and residue formation caused by exposure of aluminum alloy film does not occur.
摘要翻译：铝互连膜具有铝合金膜，钨膜和氮化钛膜的三层结构。铝互连膜和铝互连膜通过形成在氧化硅膜中的通孔电连接，一个实施例使用用于电连接的钨塞。由于氮化钛膜的光反射率低，所以即使在光不规则地反射的步骤上进行光刻，也可以将抗蚀剂的露出面积保持在规定的面积内。因此，即使在台阶上方形成通孔，也可以形成所需尺寸的通孔。即使在形成通孔时蚀刻和去除氮化钛膜，由于氧化硅膜的蚀刻速度比钨膜的蚀刻速度慢得多，因此铝合金膜不暴露。不会发生由铝合金膜暴露引起的变性层形成和残留物形成的问题。

3. 发明授权

US5313100A Multilayer interconnection structure for a semiconductor device 失效
标题翻译：半导体器件的多层互连结构
公开(公告)号：US5313100A
公开(公告)日：1994-05-17
申请号：US871228
申请日：1992-04-20
申请人： Atsushi Ishii , Yoshifumi Takata , Akihiko Ohsaki , Kazuyoshi Maekawa
发明人： Atsushi Ishii , Yoshifumi Takata , Akihiko Ohsaki , Kazuyoshi Maekawa
IPC分类号： H01L23/522 , H01L21/768 , H01L23/532 , H01L29/400 , H01L29/460
CPC分类号： H01L23/53223 , H01L2924/0002 , Y10S257/915
摘要： An aluminum interconnection film has a three layered structure of an aluminum alloy film, a tungsten film, and a titanium nitride film. An aluminum interconnection film and an aluminum interconnection film are electrically connected through a through hole formed in a silicon oxide film. Because light reflectivity of the titanium nitride film is low, the exposed area of the resist can be kept within a predetermined area even if photolithography is carried out above a step where light is irregularly reflected. Therefore, it is possible to form a through hole of a desired dimension even if the through hole is formed above the step. Even if the titanium nitride film is etched and removed in forming the through hole, the aluminum alloy film is not exposed since the etching speed of the silicon oxide film is considerably slower than that of the tungsten film. The problem of denatured layer formation and residue formation caused by exposure of aluminum alloy film does not occur.
摘要翻译：铝互连膜具有铝合金膜，钨膜和氮化钛膜的三层结构。铝互连膜和铝互连膜通过形成在氧化硅膜中的通孔电连接。由于氮化钛膜的光反射率低，所以即使在光不规则地反射的步骤上进行光刻，也可以将抗蚀剂的露出面积保持在规定的面积内。因此，即使在台阶上方形成通孔，也可以形成所需尺寸的通孔。即使在形成通孔时蚀刻和去除氮化钛膜，由于氧化硅膜的蚀刻速度比钨膜的蚀刻速度慢得多，因此铝合金膜不暴露。不会发生由铝合金膜暴露引起的变性层形成和残留物形成的问题。

4. 发明授权

US5565708A Semiconductor device comprising composite barrier layer 失效
标题翻译：包括复合阻挡层的半导体器件
公开(公告)号：US5565708A
公开(公告)日：1996-10-15
申请号：US440808
申请日：1995-05-15
申请人： Akihiko Ohsaki , Sumio Yamaguchi , Atsushi Ishii , Kazuyoshi Maekawa , Masahiko Fujisawa
发明人： Akihiko Ohsaki , Sumio Yamaguchi , Atsushi Ishii , Kazuyoshi Maekawa , Masahiko Fujisawa
IPC分类号： H01L21/28 , C23C14/06 , C23C14/18 , C23C14/58 , H01L21/203 , H01L21/205 , H01L21/285 , H01L21/768 , H01L23/485 , H01L23/522 , H01L23/532 , H01L23/48 , H01L29/46 , H01L29/54 , H01L29/62
CPC分类号： C23C14/5806 , C23C14/0641 , C23C14/185 , H01L21/28518 , H01L21/76843 , H01L21/76846 , H01L21/76855 , H01L21/76856 , H01L23/485 , H01L23/53257 , H01L2924/0002 , Y10S257/915
摘要： A semiconductor device comprising conductors electrically connected through a contact hole interlayer insulation layer with a trilayer barrier layer comprising a titanium silicide layer, titanium silicide layer formed on the titanium silicide by collimation sputtering, and a thermally nitrided titanium formed on the titanium nitride layer. The use of a trilayer barrier layer enables through the capacity of the collimation sputtering apparatus to be increased, prevents particles from occurring, and formation of a low resistance electrical connection between conductors, in addition to preventing diffusion from the titanium nitride layer and the second titanium layer to the thermally nitrided titanium layer, and between conductors.
摘要翻译：一种半导体器件，包括通过接触孔层间绝缘层与通过准直溅射形成在硅化钛上的钛硅化物层，硅化钛层和形成在氮化钛层上的热氮化钛的三层势垒层电连接的导体。除了防止从氮化钛层和第二钛的扩散之外，使用三层阻挡层能够增加准直溅射装置的容量，防止颗粒发生，以及形成导体之间的低电阻电连接层到热氮化钛层和导体之间。

5. 发明授权

US08432037B2 Semiconductor device with a line and method of fabrication thereof 有权
标题翻译：具有线的半导体器件及其制造方法
公开(公告)号：US08432037B2
公开(公告)日：2013-04-30
申请号：US13419053
申请日：2012-03-13
申请人： Kazuyoshi Maekawa , Kenichi Mori
发明人： Kazuyoshi Maekawa , Kenichi Mori
IPC分类号： H01L23/48
CPC分类号： H01L23/485 , H01L21/76805 , H01L21/76808 , H01L21/76814 , H01L21/76844 , H01L21/76849 , H01L21/76862 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.
摘要翻译：半导体器件包括层间绝缘膜，设置在层间绝缘膜中的底层线，覆盖层间绝缘膜的衬里膜，覆盖衬垫膜的层间绝缘膜。底线具有较低的孔，衬里膜和层间绝缘膜具有与下孔连通的上孔，下孔的直径大于上孔。半导体器件还包括设置在下孔内壁表面的导电膜，沿着上孔的内壁表面设置的阻挡金属和填充上孔和下孔的Cu膜。导电膜含有与阻挡金属物质相同的物质。因此可以获得高可靠性的半导体器件。

6. 发明授权

US08125085B2 Semiconductor device having wiring with oxide layer of impurity from the wiring 有权
标题翻译：具有布线的布线的半导体器件具有来自布线的杂质的氧化物层
公开(公告)号：US08125085B2
公开(公告)日：2012-02-28
申请号：US12481234
申请日：2009-06-09
申请人： Kazuyoshi Maekawa , Kenichi Mori , Kazuyuki Omori , Yuki Koyama
发明人： Kazuyoshi Maekawa , Kenichi Mori , Kazuyuki Omori , Yuki Koyama
IPC分类号： H01L23/48 , H01L29/80 , H01L21/3205 , H01L21/768
CPC分类号： H01L21/2855 , H01L21/76805 , H01L21/76832 , H01L21/76834 , H01L21/76843 , H01L21/76864 , H01L21/76873 , H01L21/76883 , H01L21/76888 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes an interlayer film formed over a semiconductor substrate. A groove is formed in the interlayer film. A wiring formed in the groove is a copper alloy including copper and a metal element. An oxide layer of the metal element is formed over the surface of the wiring. The oxide layer is formed in a first region along a grain boundary of a copper crystal and a second region surrounded by the grain boundary, over the surface of the wiring. The oxide layer formed in the first region has a thickness greater than that of the oxide layer formed in the second region.
摘要翻译：半导体器件包括形成在半导体衬底上的层间膜。在中间膜中形成凹槽。形成在槽中的布线是包括铜和金属元素的铜合金。金属元件的氧化物层形成在布线的表面上。在布线的表面上，沿着铜晶的晶界的第一区域和由晶界包围的第二区域形成氧化物层。形成在第一区域中的氧化物层的厚度大于在第二区域中形成的氧化物层的厚度。

7. 发明授权

US07564133B2 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07564133B2
公开(公告)日：2009-07-21
申请号：US11396645
申请日：2006-04-04
申请人： Masakazu Hamada , Kazuyoshi Maekawa , Kenichi Mori
发明人： Masakazu Hamada , Kazuyoshi Maekawa , Kenichi Mori
IPC分类号： H01L23/40
CPC分类号： H01L21/76865 , H01L21/76805 , H01L21/76807 , H01L21/76843
摘要： A semiconductor device comprises: a lower interconnect formed over a semiconductor substrate; an insulating film formed on the lower interconnect; a via hole penetrating the insulating film to reach the lower interconnect; a first barrier film covering bottom and side surfaces of the via hole; and a metal film filling the via hole covered with the first barrier film. A portion of the first barrier film covering a lower end of the side surface of the via hole is thicker than a portion covering the bottom surface of the via hole.
摘要翻译：半导体器件包括：形成在半导体衬底上的下部互连; 形成在下互连上的绝缘膜; 通孔穿过绝缘膜以到达下互连; 覆盖所述通孔的底面和侧面的第一阻挡膜; 以及填充由第一阻挡膜覆盖的通孔的金属膜。覆盖通孔侧面的下端的第一阻挡膜的一部分比覆盖通孔底面的部分厚。

8. 发明申请

US20080064196A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
公开(公告)号：US20080064196A1
公开(公告)日：2008-03-13
申请号：US11936138
申请日：2007-11-07
申请人： Kazuyoshi Maekawa
发明人： Kazuyoshi Maekawa
IPC分类号： H01L21/4763
CPC分类号： H01L21/265 , H01L21/26506 , H01L21/28044 , H01L21/28061 , H01L29/4941 , H01L29/518 , H01L29/78
摘要： An electrode on a semiconductor substrate includes a polysilicon layer, a silicon-implanted layer on the polysilicon layer, a tungsten nitride layer on the silicon-implanted layer, a tungsten nitride layer on the silicon-implanted layer, and a tungsten layer on the tungsten nitride layer. The layer between the polysilicon layer and the tungsten nitride layer may be either a tungsten silicon nitride layer or a silicon-germanium layer.

9. 发明授权

US6002175A Semiconductor device with improved connection hole for embedding an electrically conductive layer portion 失效
标题翻译：具有改进的用于嵌入导电层部分的连接孔的半导体器件
公开(公告)号：US6002175A
公开(公告)日：1999-12-14
申请号：US618304
申请日：1996-03-18
申请人： Kazuyoshi Maekawa
发明人： Kazuyoshi Maekawa
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L23/54 , H01L23/48
CPC分类号： H01L23/5226 , H01L21/76804 , H01L2924/0002
摘要： A semiconductor device comprising a first electrically conductive layer formed on a semiconductor element or on one main surface of a semiconductor substrate, an insulating layer formed on said first electrically conductive layer through which a connection hole of which diameter is the smallest in a portion other than the bottom is formed, and a second electrically conductive layer formed on said insulating layer.
摘要翻译：一种半导体器件，包括形成在半导体元件上或在半导体衬底的一个主表面上的第一导电层，形成在所述第一导电层上的绝缘层，通过所述绝缘层，在除了所述第一导电层之外的部分中直径最小的连接孔形成底部，形成在所述绝缘层上的第二导电层。

10. 发明申请

US20090236747A1 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090236747A1
公开(公告)日：2009-09-24
申请号：US12382624
申请日：2009-03-19
申请人： Junichi Koike , Yoshito Fujii , Jun Iijima , Noriyoshi Shimizu , Kazuyoshi Maekawa , Koji Arita , Ryotaro Yagi , Masaki Yoshimaru
发明人： Junichi Koike , Yoshito Fujii , Jun Iijima , Noriyoshi Shimizu , Kazuyoshi Maekawa , Koji Arita , Ryotaro Yagi , Masaki Yoshimaru
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L21/76853 , H01L21/288 , H01L21/76834 , H01L21/76849 , H01L21/76856 , H01L21/76861 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A multilevel interconnect structure in a semiconductor device comprises a first insulating layer (2) formed on a semiconductor wafer (1), a Cu interconnect layer (4) formed on the first insulating layer (2), a second insulating layer (6) formed on the Cu interconnect layer (4), and a metal oxide layer (5) formed at an interface between the Cu interconnect layer (4) and the second insulating layer (6). The metal oxide layer (5) is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer (4) and then heat-treating the plated layer in an oxidizing atmosphere.
摘要翻译：半导体器件中的多层互连结构包括形成在半导体晶片（1）上的第一绝缘层（2），形成在第一绝缘层（2）上的Cu互连层（4），形成第二绝缘层（6）在Cu互连层（4）上形成的金属氧化物层（5）形成在Cu互连层（4）与第二绝缘层（6）之间的界面处。通过在Cu互连层（4）上浸渍诸如Sn或Zn的金属，然后在氧化气氛中对镀层进行热处理，形成金属氧化物层（5）。

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