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1. 发明授权

US4135630A Centering device for automatic placement of chip components in hybrid circuits 失效
标题翻译：用于芯片组件自动放置在混合电路中的定心装置
公开(公告)号：US4135630A
公开(公告)日：1979-01-23
申请号：US858544
申请日：1977-12-08
申请人： Michael D. Snyder , Erwin F. Bates
发明人： Michael D. Snyder , Erwin F. Bates
IPC分类号： H01L21/683 , H05K13/04 , H01L21/58 , H01L21/96
CPC分类号： H05K13/0413 , H01L21/6838 , Y10T29/53178
摘要： A device for centering chip components attached to the tip of a pick and place spindle after selection from storage and prior to placement on a substrate. The need for precisely stored component chips is eliminated. A vacuum in the hollow spindle tip holds the component chip, while, in turn, cam-driven feet and fingers attached to the spindle housing push the component chip to a centered position on the spindle.
摘要翻译：一种用于将芯片组件定中心的装置，该芯片组件在选择存储之后并且放置在基板上之前将其安装到拾取头的尖端并放置心轴。消除了精确存储的组件芯片的需要。中空主轴尖端中的真空保持部件芯片，而依次连接到主轴壳体的凸轮驱动的脚和指将推动元件芯片到主轴上的中心位置。

2. 发明授权

US4212684A CISFET Processing including simultaneous doping of silicon components and FET channels 失效
标题翻译： CISFET处理包括同时掺杂硅元件和FET通道
公开(公告)号：US4212684A
公开(公告)日：1980-07-15
申请号：US962423
申请日：1978-11-20
申请人： Ronald W. Brower
发明人： Ronald W. Brower
IPC分类号： H01L21/02 , H01L21/033 , H01L21/3215 , H01L21/336 , H01L21/768 , H01L21/8234 , H01L21/8246 , H01L27/088 , H01L29/78 , B01J17/00 , H01L11/14 , H01L21/96
CPC分类号： H01L27/11568 , H01L21/033 , H01L21/32155 , H01L21/768 , H01L21/8234 , H01L27/088 , H01L28/20 , H01L29/66833
摘要： A process for forming a CIS (conductor-insulator-semiconductor) integrated circuit having one or more field-effect memory transistors, and one or more polysilicon resistors and/or polysilicon conductors. The polysilicon components are formed to predetermined sizes, as needed, so that the implant used to establish the memory threshold voltage of the transistor also provides the desired polysilicon resistance value(s). The process may be used to simultaneously form both memory and non-memory transistors.
摘要翻译：一种用于形成具有一个或多个场效应存储晶体管的CIS（导体 - 绝缘体 - 半导体）集成电路和一个或多个多晶硅电阻器和/或多晶硅导体的工艺。根据需要，将多晶硅部件形成为预定尺寸，使得用于建立晶体管的存储器阈值电压的注入也提供期望的多晶硅电阻值。该过程可以用于同时形成存储器和非存储器晶体管。

3. 发明授权

US4266334A Manufacture of thinned substrate imagers 失效
标题翻译：薄化衬底成像器的制造
公开(公告)号：US4266334A
公开(公告)日：1981-05-12
申请号：US98699
申请日：1979-11-29
申请人： Thomas W. Edwards , Ronald S. Pennypacker
发明人： Thomas W. Edwards , Ronald S. Pennypacker
IPC分类号： H01J9/233 , H01L21/306 , H01L21/308 , H01L21/339 , H01L27/148 , H01L29/762 , H01L21/96
CPC分类号： H01L21/30604 , H01L21/308 , H01L27/1464 , H01L27/14687 , H01L27/14692 , Y10S438/977
摘要： The front surface of a semiconductor wafer and the peripheral edge of the back surface of the wafer are protected by either coating them or by placing the wafer in a special fixture. The so protected wafer is then placed in a chemical bath and thinned to the desired thickness over the entire center region of the back surface. Then a sheet of glass which fits into the thin region within the unthinned rim on the back surface is glued to the back surface to provide a laminated structure. Next, the individual imager devices are separated from one another by cutting through the glass and thinned substrate along lines between the devices.
摘要翻译：半导体晶片的前表面和晶片的后表面的周边边缘通过涂覆它们或通过将晶片放置在专用夹具中来保护。然后将如此保护的晶片放置在化学浴中并在后表面的整个中心区域上变薄至所需厚度。然后，在后表面上的未涂覆的轮辋内的薄的区域中的玻璃板粘合到背面以提供层压结构。接下来，通过沿着装置之间的线切割穿过玻璃和变薄的衬底，各个成像器件彼此分离。

4. 发明授权

US4754544A Extremely lightweight, flexible semiconductor device arrays 失效
标题翻译：极其轻便，灵活的半导体器件阵列
公开(公告)号：US4754544A
公开(公告)日：1988-07-05
申请号：US913046
申请日：1986-09-29
申请人： Joseph J. Hanak
发明人： Joseph J. Hanak
IPC分类号： H01L27/142 , H01L31/0392 , H01L31/048 , H01L31/20 , H01L21/56 , H01L21/96 , H01L31/18
CPC分类号： H01L31/206 , H01L31/03921 , H01L31/046 , H01L31/0463 , H01L31/0465 , H01L31/048 , Y02E10/50 , Y02P70/521 , Y10S438/928
摘要： An extremely lightweight, interconnected array of semiconductor devices, such as solar cells, is formed from a large continuous area of semiconductor material disposed on an unconventionally thin, electrically conducting substrate. The interconnections are formed by removing portions of the substrate to form substrate islands underlying a layer of semiconductor material which underlies a transparent conductive oxide. The oxide layer may likewise be formed into mutually isolated islands that overlay the areas between the substrate islands. Individual units or cells so formed may be interconnected by depositing a conducting material on, alongside and at least partially between islands of oxide and/or semiconductor, by depositing a metal grid on the oxide layer and burning conducting paths to the substrate islands, or by piercing the layers and disposing a conducting material in the holes pierced.The unconventionally thin substrate may be a sheet of electroformed nickel or other thin metal or an initially thick substrate that is thinned by chemical etching after other array processing steps are completed. An encapsulant is preferably applied to the exposed surface of the semiconducting material to protect it while the substrate is being thinned or removed. Subsequently, an encapsulant is applied to the rear of substrate side of the array.
摘要翻译：半导体器件（例如太阳能电池）的非常轻量的互连阵列由设置在非常规薄导电衬底上的大的半导体材料连续区域形成。通过去除衬底的部分以形成在透明导电氧化物下面的半导体材料层下面的衬底岛形成互连。氧化物层同样可以形成为覆盖衬底岛之间的区域的相互隔离的岛。如此形成的单个单元或单元可以通过在氧化物层和/或半导体岛之间并且至少部分地在氧化物和/或半导体岛之间沉积导电材料而相互连接，通过在氧化物层上沉积金属栅格并且燃烧到基板岛的导电路径，或者通过刺穿层并在穿孔的孔中布置导电材料。非常规薄的衬底可以是电铸镍或其它薄金属片或初始厚的衬底，其在完成其它阵列处理步骤之后通过化学蚀刻而变薄。优选地，将密封剂施加到半导体材料的暴露表面，以在衬底被减薄或移除的同时对其进行保护。随后，将密封剂施加到阵列的衬底侧的后部。

5. 发明授权

US4413404A Process for manufacturing a tear strip planarization ring for gang bonded semiconductor device interconnect tape 失效
标题翻译：制造用于组合键合半导体器件互连带的撕带平面化环的方法
公开(公告)号：US4413404A
公开(公告)日：1983-11-08
申请号：US291197
申请日：1981-08-10
申请人： Carmen D. Burns
发明人： Carmen D. Burns
IPC分类号： H01L21/60 , H01L23/495 , H01L21/92 , H01L21/96 , H01L21/98
CPC分类号： H01L24/86 , H01L23/49541 , H01L23/49548 , H01L2924/01029 , H01L2924/01043 , H01L2924/01079 , H01L2924/01082 , Y10T29/49121
摘要： In an automatic assembly tape for semiconductor device assembly a continuous tape includes a plurality of sequential metal finger patterns. Each pattern includes a plurality of fingers that extend inwardly to form an array that mates with the bonding pads on a semiconductor device chip. The fingers are bonded to the chip pads so that the chip is then associated with the tape and therefore amenable to further assembly on high speed machines on a reel-to-reel tape handling basis. Each finger pattern includes an inner tear strip ring that initially holds the fingers together in a unitary structure. The fingers are joined to the ring via intermediate weakened regions. After the fingers are bonded to the chip pads, the ring is torn away so as to separate at the weakened regions. Prior to bonding, the fingers are held in precise location and in a common plane. This allows close spaced complex finger patterns and avoids bent fingers which can cause bond failure and possibly clogging of the auto assembly machines.
摘要翻译：在用于半导体器件组件的自动组装带中，连续带包括多个连续的金属指形图案。每个图案包括向内延伸以形成与半导体器件芯片上的接合焊盘配合的阵列的多个指状物。指状物结合到芯片焊盘，使得芯片然后与带相关联，并且因此适于在卷对卷磁带处理的基础上在高速机器上进一步组装。每个指形图案包括内部撕裂带环，其最初将手指保持在一体的结构中。手指通过中间弱化区域连接到环上。在将指状物粘合到芯片焊盘之后，环被撕开以在弱化区域分离。在粘合之前，手指被保持在精确的位置并且在共同的平面中。这允许紧密间隔的复杂指状图案并且避免弯曲的指状物，其可能导致粘合失效并且可能堵塞自动组装机器。

6. 发明授权

US4080718A Method of modifying electrical characteristics of MOS devices using ion implantation 失效
标题翻译：使用离子注入改善MOS器件的电气特性的方法
公开(公告)号：US4080718A
公开(公告)日：1978-03-28
申请号：US750368
申请日：1976-12-14
申请人： Paul Richman
发明人： Paul Richman
IPC分类号： H01L27/112 , G11C17/00 , G11C17/08 , H01L21/265 , H01L21/339 , H01L21/8236 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L29/762 , H01L29/78 , H01L29/788 , H01L29/792 , H01L21/96
CPC分类号： H01L27/1126 , H01L21/8236 , Y10S438/958
摘要： A method is disclosed for selectively modifying the electrical characteristics of MOS devices at a late stage in the fabrication process to form, for example, the "1" and "0" data locations of a ROM, or to form enhancement-and depletion-mode devices. In one embodiment of the method, in addition to forming openings in the passivation layer to define location of bonding pads, additional openings are formed in that layer at locations at which a data bit of one of the two levels is to be formed. Subsequently, an ion implantation is performed through the exposed underlying polysilicon gate structure to create an implantation layer at the channel regions of selected MOS devices, and thereby permanently alter the threshold voltages of these MOS devices. Other embodiments of the invention are disclosed in which ion implantation is performed through openings selectively formed in other layers, thereby to form implantation regions at selected locations to modify selected MOS devices at those locations.
摘要翻译：公开了一种方法，用于在制造过程中的后期选择性地修改MOS器件的电气特性，以形成例如ROM的“1”和“0”数据位置，或者形成增强和耗尽模式设备。在该方法的一个实施例中，除了在钝化层中形成开口以限定接合焊盘的位置之外，在要形成两个电平之一的数据位的位置处，在该层中形成另外的开口。随后，通过暴露的下面的多晶硅栅极结构进行离子注入，以在选定的MOS器件的沟道区产生注入层，从而永久地改变这些MOS器件的阈值电压。公开了本发明的其它实施例，其中通过在其它层中选择性地形成的开口进行离子注入，从而在选定位置形成注入区，以在这些位置修饰所选择的MOS器件。

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