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1. 发明授权

US06623651B2 Circuit board and a method for making the same 失效
标题翻译：电路板及其制作方法
公开(公告)号：US06623651B2
公开(公告)日：2003-09-23
申请号：US09815364
申请日：2001-03-22
申请人： Bharat Patel , Jay D. Baker , Mohan Paruchuri
发明人： Bharat Patel , Jay D. Baker , Mohan Paruchuri
IPC分类号： H01B1300
CPC分类号： H05K3/44 , H05K3/0047 , H05K3/06 , H05K3/062 , H05K3/064 , H05K3/4038 , H05K3/4069 , H05K3/429 , H05K3/445 , H05K3/4608 , H05K3/4611 , H05K3/4614 , H05K3/462 , H05K3/4623 , H05K3/4641 , H05K3/4647 , H05K3/4652 , H05K3/4685 , H05K2201/0305 , H05K2201/0352 , H05K2201/0355 , H05K2201/0361 , H05K2201/0379 , H05K2201/0397 , H05K2201/09309 , H05K2201/09509 , H05K2201/09554 , H05K2201/09609 , H05K2201/09845 , H05K2201/09881 , H05K2203/0369 , H05K2203/066 , H05K2203/0733 , H05K2203/1152 , H05K2203/1184 , H05K2203/1536
摘要： A method 10 for making a multi-layer electronic circuit board 98 having at least one electrically conductive protuberance 15 which forms a “via” and which traverses through the various layers of the electric circuit board 98, and further having at least one interconnection portion 102 which supports a wide variety of components and interconnection assemblies.
摘要翻译：一种用于制造多层电子电路板98的方法10，该多层电子电路板98具有形成“通孔”的至少一个导电突起15，并穿过电路板98的各个层，并且还具有至少一个互连部分102 其支持各种组件和互连组件。

2. 发明授权

US06555015B1 Multi-layer printed circuit board and method of making same 失效
公开(公告)号：US06555015B1
公开(公告)日：2003-04-29
申请号：US09712838
申请日：2000-11-09
申请人： Daniel Phillip Dailey , Robert Edward Belke, Jr. , Jay DeAvis Baker , Achyuta Achari , Myron Lemecha , Michael George Todd
发明人： Daniel Phillip Dailey , Robert Edward Belke, Jr. , Jay DeAvis Baker , Achyuta Achari , Myron Lemecha , Michael George Todd
IPC分类号： H01B1300
CPC分类号： H05K3/4092 , H05K3/4685
摘要： Method of manufacturing a multi-layer printed circuit board adapted for reduce interfacial sheer stresses includes a laminate substrate having a top layer forming a first major surface, a middle layer having a predetermined thickness and a bottom layer forming a second major surface opposed to the first major surface. Etch resists are disposed on the first and second surfaces corresponding to reverse images of desired conductor patterns. The first and second surfaces are thereafter etched and the photoresist removed. The laminate substrate is secured via a low modules adhesive layer to a major surface of a base. The middle layer of the laminate substrate is thereafter selectively etched so as to isolate selected portions of the first and second surfaces and to define inner connect regions therebetween having a height equal to the predetermined thickness.

3. 发明授权

US06471878B1 Method for forming a radio frequency responsive target and apparatus for verifying the authenticity of same 失效
标题翻译：用于形成无线电频率响应目标的方法和用于验证其真实性的装置
公开(公告)号：US06471878B1
公开(公告)日：2002-10-29
申请号：US09328651
申请日：1999-06-09
申请人： Morton Greene , G. William Hurley
发明人： Morton Greene , G. William Hurley
IPC分类号： H01B1300
CPC分类号： G08B13/2445 , G01S13/753 , G01S13/767 , G06F21/35
摘要： A method for forming a radio frequency responsive target formed of a pattern of thin dipoles, each of which has a position and angular orientation within the pattern, which produce a composite analog radio frequency signal in response to an interrogating signal. A first metallic film layer is deposited on top of a non-conductive substrate, an etchant resistant pattern correspondent to the thin dipole pattern is deposited on top of the first metallic film layer, and a second metallic layer occupying the first metallic layer in at least one area without etchant is applied on top of the first metallic film layer. The etchant resistant pattern is removed to expose portions of the first metallic film layer, and the second metallic layer and the exposed portions of the first metallic film layer are etched simultaneously.
摘要翻译：一种用于形成射频响应目标的方法，所述射频响应目标由薄偶极子的图案形成，每个薄型偶极子在图案内具有位置和角度取向，其响应于询问信号产生复合模拟射频信号。第一金属膜层沉积在非导电衬底的顶部上，对应于薄偶极图案的耐蚀刻图案沉积在第一金属膜层的顶部上，并且至少占据第一金属层的第二金属层没有蚀刻剂的一个区域被施加在第一金属膜层的顶部上。去除耐蚀刻图案以暴露第一金属膜层的部分，并且同时蚀刻第二金属层和第一金属膜层的暴露部分。

4. 发明授权

US06436300B2 Method of manufacturing electronic components 失效
公开(公告)号：US06436300B2
公开(公告)日：2002-08-20
申请号：US09124776
申请日：1998-07-30
申请人： Eric J. Woolsey , Douglas G. Mitchell , George F. Carney , Francis J. Carney, Jr. , Cary B. Powell
发明人： Eric J. Woolsey , Douglas G. Mitchell , George F. Carney , Francis J. Carney, Jr. , Cary B. Powell
IPC分类号： H01B1300
CPC分类号： C23F1/26 , H01L21/32134 , H01L24/11 , H01L2224/0347 , H01L2224/0361 , H01L2224/03912 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05568 , H01L2224/1147 , H01L2224/13099 , H01L2924/01004 , H01L2924/01011 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14
摘要： A method of manufacturing electronic components includes disposing a top metal layer (502) comprised of solder over a bottom metal layer (201, 202) comprised of titanium or tungsten, and selectively etching the bottom metal layer (201, 202) over the top metal layer (502) with an etchant mixture (601) comprised of an etchant, an additive to control the temperature of the etchant mixture (601), and another additive to reduce the redeposition of the top layer (502).

5. 发明授权

US06409930B1 Lamination of circuit sub-elements while assuring registration 失效
标题翻译：电路子元件的层叠，同时确保注册
公开(公告)号：US06409930B1
公开(公告)日：2002-06-25
申请号：US09432475
申请日：1999-11-01
申请人： Donald A. Whitehurst , Paul D. Wyatt , Jose F. Brenes , Jeffrey M. Borning , Bruce A. Finger
发明人： Donald A. Whitehurst , Paul D. Wyatt , Jose F. Brenes , Jeffrey M. Borning , Bruce A. Finger
IPC分类号： H01B1300
CPC分类号： H05K3/067 , C23F1/02 , C23F1/36 , C23F1/44 , H01L21/32134 , H05K3/061 , H05K3/4685 , H05K2201/0338 , H05K2203/0361 , H05K2203/0384 , H05K2203/1476
摘要： A process for the formation of an article having multiple electrical circuits comprises: providing a first sub-element comprising in sequence a first metal layer of copper in electrical contact with a second metal layer of aluminum in electrical contact with a third metal layer of copper; etching an electrical circuit design in the first metal layer and in a separate etch step, etching away at least 10%, but less than 100% of the second metal layer to provide electrical connections between the first metal layer and the third metal layer; etching an electrical circuit design into the third metal layer; adhering an etched surface comprising the circuit design of the first or third metal layer to a first surface of a support layer to form a circuit board. The process may etch the first and third metal layers simultaneously or sequentially. After adhering an etched surface comprising the circuit design of the first or third metal layer in registration to a support layer to form a circuit board, an additional step may be performed, which additional step is selected from the group consisting of: a) adhering an etched surface of a second tri-metal subelement to a second surface of the support layer and b) adhering a second support layer to said third or first metal layer, respectively, and adhering an etched surface of a second tri-metal subelement to the second support layer. The registration between layers may be effected by visual, mechanical, optical or electronic systems with visually or mechanically readable registration marks, radiation through holes, and/or posts used for identifying positions of desired registration between layers.
摘要翻译：用于形成具有多个电路的制品的方法包括：提供第一子元件，其顺序地包括与第三金属铜层电接触的与铝的第二金属层电接触的第一金属铜层; 在第一金属层中蚀刻电路设计，并且在单独的蚀刻步骤中，蚀刻掉第二金属层的至少10％但小于100％，以提供第一金属层和第三金属层之间的电连接;蚀刻将电路设计成第三金属层;将包含第一或第三金属层的电路设计的蚀刻表面粘附到支撑层的第一表面以形成电路板。该方法可以同时或顺序蚀刻第一和第三金属层。在将包括第一或第三金属层的电路设计的蚀刻表面粘附到支撑层以形成电路板之后，可以执行附加步骤，该附加步骤选自以下组中：a）将第二三金属子元件的蚀刻表面分别提供到支撑层的第二表面，b）分别将第二支撑层粘附到所述第三或第一金属层，并将第二三金属子元件的蚀刻表面粘附到第二支撑层之间的配准可以通过视觉，机械，光学或电子系统实现，其具有用于识别层之间期望的配准位置的视觉或机械可读配准标记，辐射通孔和/或柱。

6. 发明授权

US06391210B2 Process for manufacturing a multi-layer circuit board 失效
标题翻译：制造多层电路板的工艺
公开(公告)号：US06391210B2
公开(公告)日：2002-05-21
申请号：US09901848
申请日：2001-07-09
申请人： Bernd K. Appelt , John M. Lauffer , Voya R. Markovich , Irving Memis , David J. Russell
发明人： Bernd K. Appelt , John M. Lauffer , Voya R. Markovich , Irving Memis , David J. Russell
IPC分类号： H01B1300
CPC分类号： H05K3/4652 , H05K3/0023 , H05K3/0035 , H05K2203/0508 , H05K2203/0554
摘要： A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry. A further process is claimed for designing a multi-level circuit board product comprising making a prototype having the above structure in which the holes are manufactured by mechanical drilling or by laser or plasma ablation, evaluating the prototype, and then manufacturing a commercial circuit board having essentially the same structure and materials of construction as the prototype, but wherein the holes are manufactured by photoimaging techniques.
摘要翻译：一种电路板，其结构包括适用于通过激光烧蚀，等离子体消融或机械钻孔技术制造通孔的永久可光成像介电材料，以及通过光成像技术。还公开了一种用于在至少一侧具有第一级电路图案的衬底上制造多电平电路的工艺。该过程包括在第一级电路图案上施加永久可光成像电介质; 将永久可光成像电介质暴露于辐射; 将导电金属层层叠到电介质上; 通过机械钻孔或通过激光或等离子体消融在导电金属层和电介质中形成孔; 以及制作二级电路图案，并用导电材料填充所述孔，以电连接所述第一和第二层电路。要求设计多级电路板产品的另一方法包括制造具有上述结构的原型，其中通过机械钻孔或通过激光或等离子体烧蚀制造孔，评估原型，然后制造商业电路板，其具有基本上与原型相同的结构和结构材料，但是其中孔通过光成像技术制造。

7. 发明授权

US06303861B1 Connector for connecting a conductor to a structural member 失效
标题翻译：用于将导体连接到结构构件的连接器
公开(公告)号：US06303861B1
公开(公告)日：2001-10-16
申请号：US09422506
申请日：1999-10-21
申请人： Daniel David Dobrinski , Keith Francis Mello
发明人： Daniel David Dobrinski , Keith Francis Mello
IPC分类号： H01B1300
CPC分类号： H01R4/186 , H01R4/64 , Y10T29/49202 , Y10T403/478 , Y10T403/7141
摘要： A grounding connector includes a frame with upper and lower arms cantilevered from a center section to form a channel adapted to receive a section of a structural steel member. The frame has a conductor receiving region in each of the cantilevered arms, each conductor receiving region being a slot extending through the frame having a longitudinal axis aligned substantially parallel to the frame. The conductor receiving slot on one side of the frame is sized to receive a conductor of a first size and the conductor receiving slot on the other side is sized to receive a conductor of a different size. The conductor receiving regions are located so that when the upper arm and the lower arm are compressed to grip the section of the structural steel member received in the channel, the conductor is crimped to the frame. In another embodiment, the upper and lower arms of the frame have opposed surfaces for engaging the flange of the structural member and at least one of the opposed surfaces has an elongated protrusion such that when the frame is caused to clasp the flange of the structural member, the protrusion provides a slight interference between the width of the U-shaped frame and the thickness of the flange of the structural member. In other instances, opposed elongated protrusions are substantially coplanar and may be aligned substantially parallel to the frame or substantially transverse of the frame.
摘要翻译：接地连接器包括框架，其具有从中心部分悬臂的上臂和下臂，以形成适于容纳结构钢构件的一部分的通道。框架在每个悬臂中具有导体接收区域，每个导体接收区域是延伸穿过框架的槽，该纵向轴线基本上平行于框架排列。在框架一侧的导体接收槽的尺寸被设计成接收第一尺寸的导体，并且另一侧的导体接收槽的尺寸被设计成接收不同尺寸的导体。导体接收区域被定位成使得当上臂和下臂被压缩以夹持容纳在通道中的结构钢构件的部分时，导体被压接到框架。在另一个实施例中，框架的上臂和下臂具有用于接合结构构件的凸缘的相对表面，并且相对的表面中的至少一个具有细长的突起，使得当框架被扣住结构构件的凸缘时，突起在U形框架的宽度和结构构件的凸缘的厚度之间提供轻微的干涉。在其他情况下，相对的细长突起基本上是共面的，并且可以基本平行于框架或基本横向于框架对准。

8. 发明授权

US06808643B2 Hybrid interconnect substrate and method of manufacture thereof 有权
公开(公告)号：US06808643B2
公开(公告)日：2004-10-26
申请号：US10336674
申请日：2003-01-06
申请人： Kwun-Yao Ho , Moriss Kung
发明人： Kwun-Yao Ho , Moriss Kung
IPC分类号： H01B1300
CPC分类号： H01L21/6835 , H01L21/4857 , H01L2221/68345 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/48465 , H05K3/0058 , H05K3/4614 , H05K3/4644 , H05K3/4682 , H05K3/4688 , H05K2201/0108 , H05K2203/016 , H05K2203/061 , H05K2203/107 , Y10T29/49128 , H01L2924/00014 , H01L2924/00
摘要： A hybrid interconnect substrate and method of manufacture thereof are disclosed. The hybrid interconnect substrate is formed by bonding a carrier substrate to a multi-level interconnect structure formed on a handle substrate. The multi-level interconnect structure is formed by deposition, photolithography and etching processes used in integrated circuit processes or in TFT-LCD technology.

9. 发明授权

US06808642B2 Method for producing multilayer substrate and electronic part, and multilayer electronic part 失效
标题翻译：多层基板和电子部件的制造方法以及多层电子部件
公开(公告)号：US06808642B2
公开(公告)日：2004-10-26
申请号：US10238677
申请日：2002-09-11
申请人： Minoru Takaya , Toshikazu Endo , Masami Sasaki
发明人： Minoru Takaya , Toshikazu Endo , Masami Sasaki
IPC分类号： H01B1300
CPC分类号： H05K1/0373 , H01F17/0006 , H01F17/0013 , H01F41/041 , H01G4/308 , H05K1/16 , H05K1/162 , H05K1/165 , H05K3/0052 , H05K3/06 , H05K3/20 , H05K3/403 , H05K3/429 , H05K3/4652 , H05K2201/0209 , H05K2201/086 , Y10T29/49124 , Y10T29/49155
摘要： This invention has an object of providing a method for producing a multilayer substrate or an electronic part wherein decrease in the thickness has been enabled without causing the problem of insufficient strength or the like in the handling, as well as the electronic part. Such object has been attained by a method for producing a multilayer substrate or an electronic part comprising the steps of adhering a conductor layer to a transfer film, patterning the conductor layer to form a predetermined pattern, placing the transfer film overlaid with the patterned conductor layer on a prepreg so that the side of the conductor layer faces the prepreg, and then adhering the transfer film to the prepreg by applying heat and pressure and peeling the transfer film to produce the prepreg having the conductor layer formed thereon; and the multilayer electronic part produced by such method.
摘要翻译：本发明的目的在于提供一种制造多层基板或电子部件的方法，其中已经实现了厚度的减小，而不会导致处理中的强度等不足的问题以及电子部件。这样的目的已经通过多层基板或电子部件的制造方法来实现，该方法包括以下步骤：将导体层粘合到转印膜上，图案化导体层以形成预定图案，将转印膜重叠在图案化导体层在预浸料坯上使导体层的一侧面向预浸料坯，然后通过施加热和压力将转印膜粘附到预浸料上，并剥离转印膜以制备其上形成有导体层的预浸料; 和通过这种方法制造的多层电子部件。

10. 发明授权

US06787048B2 Method for producing thin bulk acoustic resonators (FBARs) with different frequencies on the same substrate by subtracting method and apparatus embodying the method 有权
标题翻译：通过减去实施该方法的方法和装置在同一基板上制造具有不同频率的薄体声波谐振器（FBAR）的方法
公开(公告)号：US06787048B2
公开(公告)日：2004-09-07
申请号：US09799202
申请日：2001-03-05
申请人： Paul D. Bradley , Richard C. Ruby , John D. Larson, III
发明人： Paul D. Bradley , Richard C. Ruby , John D. Larson, III
IPC分类号： H01B1300
CPC分类号： H03H9/564 , H03H3/04 , H03H2003/0428 , H03H2003/0471 , H04R17/10
摘要： A method for fabricating a resonator, and in particular, a thin film bulk acoustic resonator (FBAR), and a resonator embodying the method are disclosed. The resonator is fabricated on a substrate by fabricating a bottom electrode layer and a piezoelectric (PZ) layer over the bottom electrode layer. A selected portion of the PZ layer is partially etched. Then, a top electrode is fabricated over the selected portion of the PZ layer.
摘要翻译：公开了一种用于制造谐振器，特别是薄膜体声波谐振器（FBAR）的方法和体现该方法的谐振器。通过在底部电极层上制造底部电极层和压电（PZ）层，在衬底上制造谐振器。部分蚀刻PZ层的选定部分。然后，在PZ层的选定部分上制造顶部电极。

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