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1. 发明授权

US3968478A Chip topography for MOS interface circuit 失效
标题翻译： MOS接口电路的芯片形貌
公开(公告)号：US3968478A
公开(公告)日：1976-07-06
申请号：US519148
申请日：1974-10-30
申请人： William D. Mensch, Jr.
发明人： William D. Mensch, Jr.
IPC分类号： G06F13/38 , G06F15/78 , H01L27/02 , G06F13/00 , H01L25/00
CPC分类号： H01L27/0207 , G06F13/38 , G06F15/7832 , H01L2924/0002
摘要： The chip architecture of an MOS peripheral interface adaptor chip includes data bus buffers arranged along one edge of the chip, peripheral interface buffers arranged along an opposite edge of the chip and a register section centrally located on the chip. Separate power supply buses are used to supply a ground voltage to the buffer and register sections. Data bus buffers are arranged to allow the pins of the enclosing semiconductor package to correspond to data bus pins of a separate microprocessor chip. Register sections are offset on the surface of the peripheral interface adaptor chip in such a way as to facilitate nesting of the conductors coupled to the buffer circuit section. Identical buffer cells and custom drawn cells are both utilized so as to optimize use of semiconductor chip area.
摘要翻译： MOS外设接口适配器芯片的芯片架构包括沿着芯片的一个边缘布置的数据总线缓冲器，沿着芯片的相对边缘布置的外围接口缓冲器和位于芯片上方的寄存器部分。单独的电源总线用于向缓冲器和寄存器部分提供接地电压。数据总线缓冲器被布置成允许封装半导体封装的引脚对应于单独的微处理器芯片的数据总线引脚。寄存器部分以外围接口适配器芯片的表面偏移，以便于耦合到缓冲电路部分的导体的嵌套。使用相同的缓冲池和定制的拉制单元，以优化半导体芯片面积的使用。

2. 发明授权

US5097413A Abort circuitry for microprocessor 失效
标题翻译：中断微处理器电路
公开(公告)号：US5097413A
公开(公告)日：1992-03-17
申请号：US469752
申请日：1990-01-17
申请人： William D. Mensch, Jr.
发明人： William D. Mensch, Jr.
IPC分类号： G06F9/318 , G06F15/78
CPC分类号： G06F15/7832 , G06F9/30185 , G06F9/30189 , G06F9/3861
摘要： An abort circuit for a microprocessor includes a circuit receiving and latching an external abort signal to produce an internal abort signal, and circuitry responsive to the internal abort signal for preventing register transfer circuitry from responding to register transfer signals during execution of a current instruction that would otherwise result in modifying information in internal non-addressable programmable registers during duration of the internal abort signal, and abort reset circuity for responding to a reset signal to cause the abort input circuitry to stop producing the internal abort signal at the end of the abort condition.
摘要翻译：用于微处理器的中止电路包括接收和锁存外部中止信号以产生内部中止信号的电路，以及响应于内部中止信号的电路，用于防止寄存器传送电路在执行当前指令期间响应寄存器传送信号，否则会在内部中止信号的持续时间内修改内部不可寻址的可编程寄存器中的信息，并且中止复位电路以响应复位信号，导致中止输入电路在中止条件结束时停止产生内部中止信号。

3. 发明授权

US4652992A Topography of integrated circuit CMOS microprocessor chip 失效
标题翻译：集成电路CMOS微处理器芯片的地形图
公开(公告)号：US4652992A
公开(公告)日：1987-03-24
申请号：US534181
申请日：1983-09-20
申请人： William D. Mensch, Jr.
发明人： William D. Mensch, Jr.
IPC分类号： G06F9/318 , G06F15/78 , G06F1/00
CPC分类号： G06F9/3017 , G06F15/7832
摘要： The topography of a CMOS microprocessor chip includes address buffer circuitry along the bottom and lower left hand edges of the chip, data bus buffers disposed along the lower right hand edge of the chip, address register circuitry and an arithmetic logic unit contained in a register section adjacent to both the address buffer circuitry and data bus buffer circuitry, register transfer circuitry adjacent to and above the register section, P channel circuitry disposed directly above the register transfer circuitry for producing sum-of-minterm signals applied to the register transfer circuitry in response to the minterm signals produced by N channel circuitry disposed adjacent to and immediately above the P channel circuitry. Status register circuitry responsive to status register control logic disposed along the top edge of the chip is positioned in the register section for direct, low capacitance connection to the internal data bus. N and P MOSFETs in the N and P channel circuitry, respectively, are aligned so that polycrystalline silicon conductors of the minterm signals terminate on the gate electrodes of P channel MOSFETs above points at which sum-of-minterm signals are coupled to the register transfer circuitry.
摘要翻译： CMOS微处理器芯片的形状包括沿着芯片的底部和左下边缘的地址缓冲器电路，沿着芯片的右下边缘设置的数据总线缓冲器，地址寄存器电路和包含在寄存器部分中的算术逻辑单元与地址缓冲器电路和数据总线缓冲器电路相邻，与寄存器部分相邻并且在寄存器部分上方的寄存器传送电路，P沟道电路直接设置在寄存器传输电路的上方，用于响应于施加到寄存器传送电路的最小信号涉及由邻近于P信道电路并且紧邻P信道电路设置的N信道电路产生的最小信号。响应于沿着芯片的顶部边缘设置的状态寄存器控制逻辑的状态寄存器电路位于寄存器部分中，用于与内部数据总线的直接，低电容连接。 N和P沟道电路中的N和P MOSFET分别对齐，使得minterm信号的多晶硅导体终止在P沟道MOSFET的栅电极上方，在这些点处，最小值信号与寄存器传输耦合电路。

4. 发明授权

US4020472A Master slave registers for interface adaptor 失效
标题翻译：接口适配器的主从寄存器
公开(公告)号：US4020472A
公开(公告)日：1977-04-26
申请号：US614114
申请日：1975-09-17
申请人： Thomas H. Bennett , Earl F. Carlow , Edward C. Hepworth , Wilbur L. Mathys , William D. Mensch, Jr. , Rodney H. Orgill , Charles I. Peddle , Michael F. Wiles
发明人： Thomas H. Bennett , Earl F. Carlow , Edward C. Hepworth , Wilbur L. Mathys , William D. Mensch, Jr. , Rodney H. Orgill , Charles I. Peddle , Michael F. Wiles
IPC分类号： G06F13/24 , G06F13/38 , G06F3/00
CPC分类号： G06F13/38 , G06F13/24
摘要： An interface adaptor suitable for use in a microprocessor system includes an input register coupled to a bidirectional data bus of the microprocessor system. The interface adaptor includes a plurality of registers, including a control register and a data register, coupled to the input register by means of an internal input bus. Each of the plurality of registers includes flip-flops which are coupled as slave flip-flops to corresponding flip-flops of the input register. The corresponding flip-flops of the input register function as master flip-flops. The interface adaptor also includes register selection logic circuitry for selecting one of the plurality of registers by electrically coupling its slave flip-flop to the corresponding master flip-flops of the input register.
摘要翻译：适用于微处理器系统的接口适配器包括耦合到微处理器系统的双向数据总线的输入寄存器。接口适配器包括多个寄存器，包括通过内部输入总线耦合到输入寄存器的控制寄存器和数据寄存器。多个寄存器中的每一个包括作为从触发器耦合到输入寄存器的相应触发器的触发器。输入寄存器的相应触发器用作主触发器。接口适配器还包括寄存器选择逻辑电路，用于通过将其从触发器电耦合到输入寄存器的相应主触发器来选择多个寄存器中的一个。

5. 发明授权

US6052792A Power management and program execution location management system for CMOS microcomputer 失效
标题翻译： CMOS微电脑的电源管理和程序执行位置管理系统
公开(公告)号：US6052792A
公开(公告)日：2000-04-18
申请号：US694094
申请日：1996-08-08
申请人： William D. Mensch, Jr.
发明人： William D. Mensch, Jr.
IPC分类号： G06F1/08 , G06F1/32
CPC分类号： G06F1/324 , G06F1/08 , G06F1/3203 , G06F1/3253 , G06F1/3275 , Y02B60/1217 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A monitor program stored in a ROM of a microcomputer chip of a computer is operated both to (1) save power by disabling all external buses, turning off power to a communication port, deselecting all external memory devices, and turning off a fast clock oscillator and clocking all operations of the microcomputer chip at a slow second frequency, and also to (2) prioritize execution of a plurality of application programs located in external memory devices and/or internal memory of the microcomputer chip while also relying on the monitor program to effectuate normal initialization procedures. The monitor program also allows efficient access to slow external memory devices by dividing down the fast clock rate produced by the oscillator to a slower rate and accessing the slow memory at the slower rate, thereby saving power.
摘要翻译：存储在计算机的微计算机芯片的ROM中的监视器程序既可以（1）通过禁用所有外部总线，关闭通信端口的电源，取消所有外部存储器件的选择以及关闭快速时钟振荡器来节省电力并以较慢的第二频率对微型计算机芯片的所有操作进行计时，并且还（2）优先执行位于微型计算机芯片的外部存储器件和/或内部存储器中的多个应用程序，同时还依赖于监视程序实现正常的初始化程序。监视程序还允许通过将振荡器产生的快速时钟速率除以较慢速率并以较慢的速率访问慢速存储器来有效地访问慢速外部存储器件，从而节省功率。

6. 发明授权

US5212800A Method and apparatus for sensing trinary logic states in a microcomputer using bus holding circuits 失效
标题翻译：用于使用总线保持电路检测微型计算机中的三态逻辑状态的方法和装置
公开(公告)号：US5212800A
公开(公告)日：1993-05-18
申请号：US849166
申请日：1992-03-10
申请人： William D. Mensch, Jr.
发明人： William D. Mensch, Jr.
IPC分类号： G06F15/78
CPC分类号： G06F15/7814
摘要： A CMOS integrated circuit microcomputer system includes circuitry for sensing trinary logic states by using a tri-state driver circuit connected to both the input and output of a binary latch having only two states, both of which produce a high output impedance. A first trinary logic level is represented by a first logic level produced and maintained on the conductor by the external device, overpowering the binary latch. A second logic state is represented by a second logic level produced and maintained on the conductor by the external device. A third trinary state is represented by an off condition of the tri-state driver, in which case the binary latch holds whatever state is produced by the microcomputer of the connector.
摘要翻译： CMOS集成电路微计算机系统包括用于通过使用三态驱动器电路来感测三态逻辑状态的电路，该三态驱动器电路连接到仅具有两个状态的二进制锁存器的输入和输出，两者都产生高输出阻抗。第一个三进制逻辑电平由外部设备在导体上产生和维持的第一逻辑电平表示，从而使二进制锁存器功能更为强大。第二逻辑状态由外部设备在导体上产生和维持的第二逻辑电平表示。第三三态由三态驱动器的关闭状态表示，在这种情况下，二进制锁存器保持连接器的微型计算机产生的任何状态。

7. 发明授权

US3991307A Integrated circuit microprocessor with parallel binary adder having on-the-fly correction to provide decimal results 失效
标题翻译：具有并行二进制加法器的集成电路微处理器具有实时校正以提供十进制结果
公开(公告)号：US3991307A
公开(公告)日：1976-11-09
申请号：US613890
申请日：1975-09-16
申请人： Charles Ingerham Peddle , Wilbur L. Mathys , William D. Mensch, Jr. , Rodney H. Orgill
发明人： Charles Ingerham Peddle , Wilbur L. Mathys , William D. Mensch, Jr. , Rodney H. Orgill
IPC分类号： G06F7/494 , G06F7/50 , G06F7/385
CPC分类号： G06F7/494 , G06F2207/4924
摘要： Disclosed is an integrated circuit microprocessor with a parallel binary adder whose output can be corrected on-the-fly to provide decimal results. The correction is by logical gating which operates selectively and on-the-fly, that is, while the sum from the output of the binary adder is being transferred to an accumulator. As a result, the same binary adder can provide the binary sum of the operands supplied to it, or the binary coded decimal sum of bcd operands, or the binary coded decimal difference of bcd operands, in a single operating cycle and without the need to recycle the sum of the operands through the adder. This single cycle correction significantly speeds up the operation of the invented microprocessor as compared to known prior art microprocessors which recycle the adder output when a binary coded decimal sum or difference is required.
摘要翻译：公开了一种具有并行二进制加法器的集成电路微处理器，其输出可以被即时校正以提供十进制结果。校正是通过有选择地和即时操作的逻辑选通，即来自二进制加法器的输出的和被传送到累加器。结果，相同的二进制加法器可以在单个操作周期中提供提供给它的操作数的二进制和或bcd操作数的二进制编码十进制和或bcd操作数的二进制编码的十进制差，并且不需要通过加法器回收操作数之和。与已知的现有技术的微处理器相比，这种单循环校正显着地加快了本发明的微处理器的运行，当需要二进制编码的十进制小数或差分时，循环加法器输出。

8. 发明授权

US5511209A Programmable microcomputer oscillator circuitry with synchronized fast and slow clock output signal 失效
标题翻译：可编程微波振荡器电路具有同步快速和慢速时钟输出信号
公开(公告)号：US5511209A
公开(公告)日：1996-04-23
申请号：US48933
申请日：1993-04-16
申请人： William D. Mensch, Jr.
发明人： William D. Mensch, Jr.
IPC分类号： G06F15/78 , G06F13/372 , G06F13/40 , G06F1/06 , G06F1/12
CPC分类号： G06F15/7814 , Y02B60/1207 , Y02B60/1225
摘要： A CMOS integrated circuit microcomputer is switchable under software control between high speed, high power operation and low speed, low power operation. The microcomputer includes asynchronous fast and slow clock oscillators. A synchronizing circuit coupled to the fast and slow clock oscillators receives a clock selection signal, and in response thereto produces a clock enable signal. The clock enable signal has the same frequency as and is synchronized with either the fast clock signal or the slow clock signal, depending on the state of the clock selection signal. The clock enable signal is input to gating circuitry that gates either the fast or the slow clock signal to provide a selectable speed clock signal to be used elsewhere in the microcomputer.
摘要翻译： CMOS集成电路微机可在高速，高功率，低功耗，低功耗操作之间的软件控制下切换。微型计算机包括异步快速和慢速时钟振荡器。耦合到快速和慢时钟振荡器的同步电路接收时钟选择信号，响应于此产生时钟使能信号。根据时钟选择信号的状态，时钟使能信号具有与快速时钟信号或慢时钟信号相同的频率并与其同步。时钟使能信号被输入到选通快速或慢时钟信号的门控电路，以提供在微计算机其他地方使用的可选速度时钟信号。

9. 发明授权

US4876639A Method and circuitry for causing sixteen bit microprocessor to execute eight bit op codes to produce either internal sixteen bit operation or internal eight bit operation in accordance with an emulation bit 失效
标题翻译：用于使16位微处理器执行8位运算代码以根据仿真位产生内部16位运算或内部8位运算的方法和电路
公开(公告)号：US4876639A
公开(公告)日：1989-10-24
申请号：US178429
申请日：1988-04-06
申请人： William D. Mensch, Jr.
发明人： William D. Mensch, Jr.
IPC分类号： G06F9/318 , G06F15/78
CPC分类号： G06F9/30174 , G06F15/7832 , G06F9/30185
摘要： A sixteen bit microprocessor includes an emulation bit that is loaded into an instruction register with 8 bit op codes. If the emulation bit is a "1", the 16 bit microprocessor operates internally as a 6502 type eight bit microprocessor, thereby emulating a 6502 microprocessor. If the emulation bit is set to a "0", the 16 bit microprocessor executes an instruction set of which the 6502 instruction set is a subset to effectuate internal 16 bit operation.
摘要翻译：十六位微处理器包括一个仿真位，该仿真位被加载到具有8位运算代码的指令寄存器中。如果仿真位为“1”，则16位微处理器内部作为6502型8位微处理器进行操作，从而仿真6502微处理器。如果仿真位设置为“0”，则16位微处理器执行指令集，其中6502指令集是子集，以实现内部16位操作。

10. 发明授权

US4739475A Topography for sixteen bit CMOS microprocessor with eight bit emulation and abort capability 失效
标题翻译：十六位CMOS微处理器的地形，具有八位仿真和中止功能
公开(公告)号：US4739475A
公开(公告)日：1988-04-19
申请号：US675831
申请日：1984-11-28
申请人： William D. Mensch, Jr.
发明人： William D. Mensch, Jr.
IPC分类号： G06F9/318 , G06F15/78 , G06F1/00 , G06F9/44 , G06F13/38 , H01L27/00
CPC分类号： G06F9/30174 , G06F15/7832 , G06F9/30189 , G06F9/30196
摘要： The topography of a sixteen bit CMOS microprocessor chip including circuitry for enabling it to emulate, under software control, a prior art 6502 microprocessor includes an N-channel minterm logic section including 498 "vertical" diffused minterm lines across which 32 "horizontal" metal lines from an instruction register and a timing generator pass and make selective contact to separate polycrystalline silicon gate electrodes to effectuate a first level of instruction op code decoding. The resulting minterm signals are inverted by a row of CMOS inverters, the outputs of which are connected to polycrystalline lines extending into an N-channel sum-of-minterm section. "Horizontal" metal sum-of-minterm conductors contact various N-channel field effect transistors in the sum-of-minterm region. Those sum-of-minterm lines having fewest field effect transistors connected thereto are positioned on the bottom of the sum-of-minterm array, and those having the most connections to N-channel FETs are positioned at the top thereof to minimize the amount of chip surface area required for the sum-of-minterm array and for routing of the sum-of-minterm signals produced thereby to transfer gate logic on the chip.
摘要翻译：包括电路的16位CMOS微处理器芯片的形状在软件控制下能够模拟现有技术的6502微处理器包括N沟道最小逻辑部分，其包括498个“垂直”扩散的最小线，跨32个“水平”金属线从指令寄存器和定时发生器通过并选择性地接触分离的多晶硅栅电极以实现第一级指令操作码解码。所产生的最小信号由一排CMOS反相器反相，其中的CMOS反相器的输出端连接到延伸到N沟道微分段的多晶线上。 “水平”金属微型导体在最小区域内接触各种N沟道场效应晶体管。具有连接到其上的具有最少的场效应晶体管的那些最小线路位于最小阵列阵列的底部，并且具有与N沟道FET的最多连接的那些线定位在其顶部以最小化芯片表面积和最小值阵列所需的芯片表面积以及由此产生的最小值信号的路由以传输芯片上的门逻辑。

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