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1. 发明申请

US20090290283A1 Scalable Integrated Circuit High Density Capacitors 有权
标题翻译：可扩展集成电路高密度电容器
公开(公告)号：US20090290283A1
公开(公告)日：2009-11-26
申请号：US12511350
申请日：2009-07-29
申请人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Ranganathan , Chao Tang , Pieter Vorenkamp
发明人： Victor Chiu-Kit Fong , Eric Bruce Blecker , Tom W. Kwan , Ning Li , Sumant Ranganathan , Chao Tang , Pieter Vorenkamp
IPC分类号： H01G4/228
CPC分类号： H01L23/5223 , H01L23/5225 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.
摘要翻译：本发明提供了几种可扩展的集成电路高密度电容器及其布局技术。电容器例如通过改变金属层的数量和/或从电容器使用的金属层的面积来缩放。电容器使用不同的金属化图案来形成金属层，以及不同的通孔图案以耦合相邻的金属层。在实施例中，可选屏蔽包括作为电容器的最顶层和/或最底层，和/或作为侧屏蔽，以减少不必要的寄生电容。

2. 发明授权

US07148750B2 Gigabit ethernet transceiver with analog front end 有权
公开(公告)号：US07148750B2
公开(公告)日：2006-12-12
申请号：US11417073
申请日：2006-05-02
申请人： Arya R. Behzad , Klaas Bult , Ramon A. Gomez , Chi-Hung Lin , Tom W. Kwan , Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
发明人： Arya R. Behzad , Klaas Bult , Ramon A. Gomez , Chi-Hung Lin , Tom W. Kwan , Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03G3/10
CPC分类号： H03F1/32 , H03F3/347 , H03F3/505 , H03F2200/211 , H03F2200/252 , H03F2200/421 , H03F2200/513 , H03G1/0088 , H03G3/001 , H03G3/3036 , H03G3/3052 , H03G5/10 , H03H11/245
摘要： Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

3. 发明授权

US07053715B2 Gigabit Ethernet transceiver with analog front end 失效
标题翻译：具有模拟前端的千兆以太网收发器
公开(公告)号：US07053715B2
公开(公告)日：2006-05-30
申请号：US11005603
申请日：2004-12-06
申请人： Arya R. Behzad , Klaas Bult , Ramon A. Gomez , Chi-Hung Lin , Tom W. Kwan , Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
发明人： Arya R. Behzad , Klaas Bult , Ramon A. Gomez , Chi-Hung Lin , Tom W. Kwan , Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03G3/10
CPC分类号： H03F1/32 , H03F3/347 , H03F3/505 , H03F2200/211 , H03F2200/252 , H03F2200/421 , H03F2200/513 , H03G1/0088 , H03G3/001 , H03G3/3036 , H03G3/3052 , H03G5/10 , H03H11/245
摘要： Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.
摘要翻译：电路从集成电路可编程增益衰减器中的信号路径中去除开关。可编程增益衰减器和可编程增益放大器通常使用半导体开关在信号电平之间切换。这种开关可能在信号中引入非线性。通过将开关与信号路径隔离，可以提高PGA的线性度。

4. 发明授权

US07019598B2 Integrated VCO having an improved tuning range over process and temperature variations 有权
公开(公告)号：US07019598B2
公开(公告)日：2006-03-28
申请号：US10665631
申请日：2003-09-22
申请人： Ralph Duncan , Tom W. Kwan
发明人： Ralph Duncan , Tom W. Kwan
IPC分类号： H03B5/04 , H03B5/12
CPC分类号： H03L7/23 , H01F17/0006 , H01F17/0013 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L27/0248 , H01L27/08 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H03B5/1209 , H03B5/1212 , H03B5/1228 , H03B5/1253 , H03B5/364 , H03B2200/0038 , H03B2201/025 , H03B2201/0266 , H03D7/161 , H03D7/18 , H03G1/0029 , H03H11/1291 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L1/023 , H03L7/10 , H01L2924/00
摘要： An integrated VCO having an improved tuning range over process and temperature variations. There is therefore provided in a present embodiment of the invention an integrated VCO. The VCO comprises, a substrate, a VCO tuning control circuit responsive to a VCO state variable that is disposed upon the substrate, and a VCO disposed upon the substrate, having a tuning control voltage input falling within a VCO tuning range for adjusting a VCO frequency output, and having its tuning range adjusted by the tuning control circuit in response to the VCO state variable.

5. 发明授权

US5732002A Multi-rate IIR decimation and interpolation filters 失效
标题翻译：多速率IIR抽取和插值滤波器
公开(公告)号：US5732002A
公开(公告)日：1998-03-24
申请号：US447746
申请日：1995-05-23
申请人： Wai L. Lee , Tom W. Kwan
发明人： Wai L. Lee , Tom W. Kwan
IPC分类号： H03H17/04 , H03H19/00 , G06F17/17 , G06F17/10
CPC分类号： H03H17/0444 , H03H17/045 , H03H19/004
摘要： A digital filtering method that includes sampling an input signal at a first rate, integrating the signal, sampling the integrated version at a different rate, and combining the sampled integrated version with the input signal. The method can include again integrating the integrated version, sampling the twice integrated version at a third rate different from the first and second rates, and combining the twice integrated version with the integrated version and the input signal. The integrated version can be again integrated, the twice integrated version can be sampled at a third rate different from the first and second rates, and the twice integrated version can be combined with the integrated version. A common circuit component can be multiplexed to participate in two integrating steps.
摘要翻译：一种数字滤波方法，其包括以第一速率对输入信号进行采样，对信号进行积分，以不同速率对集成版本进行采样，以及将采样的集成版本与输入信号进行组合。该方法可以包括再次集成集成版本，以与第一和第二速率不同的第三速率对两次集成版本进行采样，并将两次集成版本与集成版本和输入信号组合。集成版本可以再次集成，可以以与第一和第二速率不同的第三速率对两次集成版本进行采样，并且两次集成版本可以与集成版本组合。公共电路组件可以被多路复用以参与两个集成步骤。

6. 发明授权

US5666299A Asynchronous digital sample rate converter 失效
标题翻译：异步数字采样率转换器
公开(公告)号：US5666299A
公开(公告)日：1997-09-09
申请号：US446036
申请日：1995-05-19
申请人： Robert W. Adams , Tom W. Kwan , Michael Coln
发明人： Robert W. Adams , Tom W. Kwan , Michael Coln
IPC分类号： H03H17/00 , H03H17/02 , H03H17/06 , G06F7/38 , G06F17/10 , G06F17/17
CPC分类号： H03H17/0628
摘要： An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise. A circuit determining the output to input sample rate ratios can also be provided to scale coefficient addresses and resulting output samples to allow for decimation. This circuit includes a form of digital hysteresis to eliminate noise. The ROM coefficients are reduced by relying on the symmetry of the impulse response of the interpolation filter and by utilizing a variable step size forward and backward linear interpolation.
摘要翻译：异步数字采样率转换器包括用于存储输入数据值的随机存取存储器和用于存储缩减的一组内插滤波器系数的只读存储器。输入数据以输入采样率写入随机存取存储器。输出样本由给定输入数据流的乘法/累加引擎提供，滤波器系数根据请求在输出频率下产生输出采样。用于从随机存取存储器读取输入数据的初始地址和来自只读存储器的系数的地址由自动定心方案提供，该自动定心方案是具有通过输入的近似馈送的数字积分器的一阶闭环系统输出采样率。这种自动对中方案可以包括用于消除稳态误差的前馈低通滤波器和内插写入地址以减少噪声。还可以提供确定输入到输入采样速率比的电路，以缩放系数地址和产生的输出采样以允许抽取。该电路包括一种消除噪声的数字滞后形式。通过依赖于内插滤波器的脉冲响应的对称性以及利用可变步长前后线性插值来减小ROM系数。

7. 发明授权

US5471411A Interpolation filter with reduced set of filter coefficients 失效
标题翻译：内插滤波器，滤波器系数减少
公开(公告)号：US5471411A
公开(公告)日：1995-11-28
申请号：US234177
申请日：1994-04-28
申请人： Robert W. Adams , Tom W. Kwan , Michael Coln
发明人： Robert W. Adams , Tom W. Kwan , Michael Coln
IPC分类号： H03H17/00 , H03H17/02 , H03H17/06 , G06F15/31
CPC分类号： H03H17/0628
摘要： An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise. A circuit determining the output to input sample rate ratios can also be provided to scale coefficient addresses and resulting output samples to allow for decimation. This circuit includes a form of digital hysteresis to eliminate noise. The ROM coefficients are reduced by relying on the symmetry of the impulse response of the interpolation filter and by utilizing a variable step size forward and backward linear interpolation.
摘要翻译：异步数字采样率转换器包括用于存储输入数据值的随机存取存储器和用于存储缩减的一组内插滤波器系数的只读存储器。输入数据以输入采样率写入随机存取存储器。输出样本由给定输入数据流的乘法/累加引擎提供，滤波器系数根据请求在输出频率下产生输出采样。用于从随机存取存储器读取输入数据的初始地址和来自只读存储器的系数的地址由自动定心方案提供，该自动定心方案是具有通过输入的近似馈送的数字积分器的第一阶闭环系统输出采样率。这种自动对中方案可以包括用于消除稳态误差的前馈低通滤波器和内插写入地址以减少噪声。还可以提供确定输入到输入采样速率比的电路，以缩放系数地址和产生的输出采样以允许抽取。该电路包括一种消除噪声的数字滞后形式。通过依赖于内插滤波器的脉冲响应的对称性以及利用可变步长前后线性插值来减小ROM系数。

8. 发明授权

US08754746B2 Hand-held gaming device that identifies user based upon input from touch sensitive panel 有权
标题翻译：手持游戏设备，根据触摸屏的输入识别用户
公开(公告)号：US08754746B2
公开(公告)日：2014-06-17
申请号：US12912458
申请日：2010-10-26
申请人： Bob Lukas , David A. Sobel , Monika Gupta , Qiang Fu , Sumant Ranganathan , Jeyhan Karaoguz , Tom W. Kwan , Xinyu Yu
发明人： Bob Lukas , David A. Sobel , Monika Gupta , Qiang Fu , Sumant Ranganathan , Jeyhan Karaoguz , Tom W. Kwan , Xinyu Yu
IPC分类号： G06F17/00 , G06F7/04 , G06F21/32 , G06F21/30 , G06F3/038 , G06F3/0488 , G06F3/041
CPC分类号： G06F21/32 , A63F13/06 , A63F2300/1012 , A63F2300/1031 , A63F2300/105 , A63F2300/1068 , A63F2300/1081 , A63F2300/401 , G06F3/0383 , G06F3/0416 , G06F3/0488 , G06F21/30
摘要： Operating a game controller to identify a user by receiving touch pad input from at least one touch sensitive pad of the game controller that has a plurality of touch sensitive elements. The touch pad input corresponds to the user's touch of at least some of the plurality of touch sensitive elements. The touch pad input is at least partially processed by processing circuitry of the game controller and transmitted to a game console via a communications interface of the game controller for processing of the at least partially processed touch pad input to identify the user via pattern recognition. At least partially processing the touch pad input can be by identifying at least one finger orientation, at least one finger spacing, at least one finger width, a plurality of finger knuckle/joint locations, and/or a plurality of finger lengths based upon the touch pad input.
摘要翻译：操作游戏控制器以通过从具有多个触敏元件的游戏控制器的至少一个触敏板接收触摸板输入来识别用户。触摸板输入对应于用户对多个触敏元件中的至少一些的触摸。触摸板输入至少部分地由游戏控制器的处理电路处理，并且经由游戏控制器的通信接口传送到游戏控制台，用于处理至少部分处理的触摸板输入以经由模式识别来识别用户。至少部分地处理触摸板输入可以通过基于所述至少一个手指定向，至少一个手指间隔，至少一个手指宽度，多个指关节/关节位置和/或多个手指长度来识别触摸板输入。

9. 发明申请

US20130076549A1 GATE LEAKAGE COMPENSATION IN A CURRENT MIRROR 有权
标题翻译：门电流泄漏补偿
公开(公告)号：US20130076549A1
公开(公告)日：2013-03-28
申请号：US13246319
申请日：2011-09-27
申请人： Ovidiu Bajdechi , Tom W. Kwan
发明人： Ovidiu Bajdechi , Tom W. Kwan
IPC分类号： H03M1/66 , G05F1/10
CPC分类号： G05F3/08 , G05F3/267 , H03M1/0607 , H03M1/66
摘要： A method and apparatus is disclosed to compensate for gate leakage currents of thin oxide devices that have very thin oxide layers in a current mirror of a digital-to-analog converter (DAC). The DAC converts a digital input signal from a digital representation in a digital signaling domain to an analog representation in an analog signaling domain to provide an analog output signal. The DAC uses one or more transistors to convert the digital input signal from the digital representation to the analog representation. These transistors are typically implemented using thin oxide devices that have very thin oxide layers and corresponding gate leakage currents that are associated with these very thin oxide layers. The current-steering DAC provides these gate leakage currents independent of its corresponding reference source without any substantial affect upon its full scale output.
摘要翻译：公开了一种用于补偿在数模转换器（DAC）的电流镜中具有非常薄的氧化物层的薄氧化物器件的栅极泄漏电流的方法和装置。 DAC将数字输入信号从数字信号域中的数字表示转换为模拟信号域中的模拟表示，以提供模拟输出信号。 DAC使用一个或多个晶体管将数字输入信号从数字表示转换为模拟表示。这些晶体管通常使用具有与这些非常薄的氧化物层相关联的非常薄的氧化物层和相应的栅极泄漏电流的薄氧化物器件来实现。电流导向DAC提供独立于其相应参考源的这些栅极泄漏电流，而对其满量程输出没有任何实质影响。

10. 发明授权

US07671681B2 Gigabit ethernet transceiver with analog front end 有权
标题翻译：具有模拟前端的千兆以太网收发器
公开(公告)号：US07671681B2
公开(公告)日：2010-03-02
申请号：US10282688
申请日：2002-10-29
申请人： Arya R. Behzad , Klaas Bult , Ramon A. Gomez , Chi-Hung Lin , Tom W. Kwan , Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
发明人： Arya R. Behzad , Klaas Bult , Ramon A. Gomez , Chi-Hung Lin , Tom W. Kwan , Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03G3/10
CPC分类号： H03F1/32 , H03F3/347 , H03F3/505 , H03F2200/211 , H03F2200/252 , H03F2200/421 , H03F2200/513 , H03G1/0088 , H03G3/001 , H03G3/3036 , H03G3/3052 , H03G5/10 , H03H11/245
摘要： Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.
摘要翻译：电路从集成电路可编程增益衰减器中的信号路径中去除开关。可编程增益衰减器和可编程增益放大器通常使用半导体开关在信号电平之间切换。这种开关可能在信号中引入非线性。通过将开关与信号路径隔离，可以提高PGA的线性度。

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