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1. 发明授权

US10261789B2 Data processing apparatus and method for controlling performance of speculative vector operations 有权
公开(公告)号：US10261789B2
公开(公告)日：2019-04-16
申请号：US14461664
申请日：2014-08-18
申请人： ARM LIMITED
发明人： Alastair David Reid , Daniel Kershaw
IPC分类号： G06F9/312 , G06F9/455 , G06F9/38 , G06F15/76 , G06F9/30 , G06F15/78
摘要： A data processing apparatus and a method of controlling performance of speculative vector operations are provided. The apparatus comprises processing circuitry for performing a sequence of speculative vector operations on vector operands, each vector operand comprising a plurality of vector elements, and speculation control circuitry for maintaining a speculation width indication indicating the number of vector elements of each vector operand to be subjected to the speculative vector operations. The speculation width indication is set to an initial value prior to performance of the sequence of speculative vector operations. The processing circuitry generates progress indications during performance of the sequence of speculative vector operations, and the speculation control circuitry detects, with reference to the progress indications and speculation reduction criteria, presence of a speculation reduction condition. The speculation reduction condition is a condition indicating that a reduction in the speculation width indication is expected to improve at least one performance characteristic of the data processing apparatus relative to continued operation without the reduction in the speculation width indication. The speculation control circuitry is responsive to detection of the speculation reduction condition to reduce the speculation width indication. This can significantly increase performance (for example in terms of throughput and/or energy consumption) when performing speculative vector operations.

2. 发明申请

US20150261512A1 INTERLEAVING DATA ACCESSES ISSUED IN RESPONSE TO VECTOR ACCESS INSTRUCTIONS 有权
标题翻译：响应向导访问指令发出数据访问
公开(公告)号：US20150261512A1
公开(公告)日：2015-09-17
申请号：US14665142
申请日：2015-03-23
申请人： ARM Limited
发明人： Alastair David Reid
IPC分类号： G06F9/45 , G06F9/30
CPC分类号： G06F8/4441 , G06F8/443 , G06F8/445 , G06F8/45 , G06F8/452 , G06F9/30 , G06F9/30036 , G06F9/30043 , G06F9/30087 , G06F9/35 , G06F9/3834 , G06F9/3838
摘要： A vector data access unit includes data access ordering circuitry, for issuing data access requests indicated by elements of earlier and a later vector instructions, one being a write instruction. An element indicating the next data access for each of the instructions is determined. The next data accesses for the earlier and the later instructions may be reordered. The next data access of the earlier instruction is selected if the position of the earlier instruction's next data element is less than or equal to the position of the later instruction's next data element minus a predetermined value. The next data access of the later instruction may be selected if the position of the earlier instruction's next data element is higher than the position of the later instruction's next data element minus a predetermined value. Thus data accesses from earlier and later instructions are partially interleaved.
摘要翻译：向量数据访问单元包括数据访问排序电路，用于发出由先前的元素和稍后的向量指令指示的数据访问请求，一个是写指令。确定指示每个指令的下一个数据访问的元素。可以重新排序对于较早的和稍后的指令的下一个数据访问。如果较早的指令的下一个数据元素的位置小于或等于后一个指令的下一个数据元素的位置减去预定值，则选择较早指令的下一个数据访问。如果较早指令的下一个数据元素的位置高于稍后指令的下一个数据元素的位置减去预定值，则可以选择后一条指令的下一个数据访问。因此，来自较早和稍后的指令的数据访问被部分交错。

3. 发明授权

US11126714B2 Encoding of input to storage circuitry 有权
公开(公告)号：US11126714B2
公开(公告)日：2021-09-21
申请号：US16149297
申请日：2018-10-02
申请人： Arm Limited
发明人： Alastair David Reid , Dominic Phillip Mulligan , Milosch Meriac , Matthias Lothar Boettcher , Nathan Yong Seng Chong , Ian Michael Caulfield , Peter Richard Greenhalgh , Frederic Claude Marie Piry , Albin Pierrick Tonnerre , Thomas Christopher Grocutt , Yasuo Ishii
IPC分类号： G06F21/55 , H04L9/06 , G06F9/38 , G06F12/10 , G06F21/53 , G06F21/78
摘要： A data processing apparatus comprises branch prediction circuitry adapted to store at least one branch prediction state entry in relation to a stream of instructions, input circuitry to receive at least one input to generate a new branch prediction state entry, wherein the at least one input comprises a plurality of bits; and coding circuitry adapted to perform an encoding operation to encode at least some of the plurality of bits based on a value associated with a current execution environment in which the stream of instructions is being executed. This guards against potential attacks which exploit the ability for branch prediction entries trained by one execution environment to be used by another execution environment as a basis for branch predictions.

4. 发明授权

US09886239B2 Exponent monitoring 有权
公开(公告)号：US09886239B2
公开(公告)日：2018-02-06
申请号：US14606510
申请日：2015-01-27
申请人： ARM LIMITED
发明人： Guy Larri , Lee Douglas Smith , David Raymond Lutz , Alastair David Reid
IPC分类号： G06F7/48 , G06F7/483 , G06F7/499 , G06F9/30 , G06F17/16 , H03M7/12 , H03M7/24 , G06F11/34 , G06F11/36 , G06F5/01 , G06F7/38 , G06F7/507 , G06F9/38 , G06F7/506
CPC分类号： G06F7/483 , G06F5/012 , G06F7/38 , G06F7/48 , G06F7/4991 , G06F7/49915 , G06F7/49921 , G06F7/49942 , G06F7/506 , G06F7/507 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30112 , G06F9/3016 , G06F9/30185 , G06F9/30192 , G06F9/3885 , G06F11/3404 , G06F11/3476 , G06F11/348 , G06F11/3636 , G06F11/3644 , G06F11/3648 , G06F17/16 , G06F2201/865 , G06F2207/483 , H03M7/12 , H03M7/24
摘要： A processing apparatus includes floating point arithmetic circuitry coupled to monitoring circuitry. The monitoring circuitry stores exponent limit data indicating at least one of a maximum exponent value and a minimum exponent value processed when performing the floating point arithmetic operations. The monitoring circuitry may be selectively enabled in dependence upon a virtual machine identifier, an application specific identifier or a program counter value range. Exponent limit data may be gathered in respect of different portions of the floating point arithmetic circuitry and/or may be aggregated to form global exponent limit data for the system.

5. 发明授权

US11385899B2 Branch prediction cache for multiple software workloads 有权
公开(公告)号：US11385899B2
公开(公告)日：2022-07-12
申请号：US17052655
申请日：2019-05-09
申请人： Arm Limited
发明人： Alastair David Reid
IPC分类号： G06F9/30 , G06F9/38
摘要： An apparatus comprises: processing circuitry 18 to process instructions from a plurality of software workloads; a branch prediction cache 40-42 to cache branch prediction state data selected from a plurality of sets of branch prediction state data 60 stored in a memory system 30, 32, 34, each set of branch prediction state data corresponding to one of said plurality of software workloads; and branch prediction circuitry 4 to predict an outcome of a branch instruction of a given software workload based on branch prediction state data cached in the branch prediction cache from the set of branch prediction state data corresponding to said given software workload. This is useful for mitigating against speculation side-channel attacks which exploit branch mispredictions caused by malicious training of a branch predictor.

6. 发明授权

US09483438B2 Apparatus and method for controlling the number of vector elements written to a data store while performing speculative vector write operations 有权
标题翻译：用于控制在执行推测矢量写入操作时写入数据存储器的向量元素的数量的装置和方法
公开(公告)号：US09483438B2
公开(公告)日：2016-11-01
申请号：US14462194
申请日：2014-08-18
申请人： ARM LIMITED
发明人： Alastair David Reid , Daniel Kershaw
IPC分类号： G06F9/38 , G06F15/78 , G06F9/30
CPC分类号： G06F15/7867 , G06F9/30036 , G06F9/30043 , G06F9/30087 , G06F9/30098 , G06F9/30109 , G06F9/3824 , G06F9/3834 , G06F9/3838 , G06F9/3842 , G06F9/3859 , G06F9/3875
摘要： A data processing apparatus and method for performing speculative vector access operations are provided. The data processing apparatus has a reconfigurable buffer accessible to vector data access circuitry and comprising a storage array for storing up to M vectors of N vectors elements. The vector data access circuitry performs speculative data write operations in order to cause vector elements from selected vector operands in a vector register bank to be stored into the reconfigurable buffer. On occurrence of a commit condition, the vector elements currently stored in the reconfigurable buffer are then written to a data store. Speculation control circuitry maintains a speculation width indication indicating the number of vector elements of each selected vector operand stored in the reconfigurable buffer. The speculation width indication is initialized to an initial value, but on detection of an overflow condition within the reconfigurable buffer the speculation width indication is modified to reduce the number of vector elements of each selected vector operand stored in the reconfigurable buffer. The reconfigurable buffer then responds to a change in the speculation width indication by reconfiguring the storage array to increase the number of vectors M and reduce the number of vector elements N per vector. This provides an efficient mechanism for supporting performance of speculative data write operations.
摘要翻译：提供了一种用于执行推测向量访问操作的数据处理装置和方法。数据处理装置具有可访问向量数据访问电路的可重构缓冲器，并且包括用于存储N个向量元素的多达M个向量的存储阵列。向量数据访问电路执行推测性数据写入操作，以便使来自向量寄存器组中的所选向量操作数的向量元素被存储到可重构缓冲器中。在发生提交条件时，当前存储在可重构缓冲器中的向量元素然后被写入数据存储。投机控制电路维持指示宽度指示，指示存储在可重构缓冲器中的每个所选向量操作数的向量元素的数量。推测宽度指示被初始化为初始值，但是通过检测可重构缓冲器内的溢出条件，推测宽度指示被修改以减少存储在可重构缓冲器中的每个所选向量操作数的向量元素的数量。然后，可重构缓冲器通过重新配置存储阵列来响应推测宽度指示的变化，以增加向量M的数量并减少每个向量的向量元素N的数量。这提供了一种有效的机制来支持投机数据写入操作的性能。

7. 发明授权

US09483243B2 Interleaving data accesses issued in response to vector access instructions 有权
公开(公告)号：US09483243B2
公开(公告)日：2016-11-01
申请号：US14665142
申请日：2015-03-23
申请人： ARM Limited
发明人： Alastair David Reid
IPC分类号： G06F9/30 , G06F9/45 , G06F9/35 , G06F9/38
CPC分类号： G06F8/4441 , G06F8/443 , G06F8/445 , G06F8/45 , G06F8/452 , G06F9/30 , G06F9/30036 , G06F9/30043 , G06F9/30087 , G06F9/35 , G06F9/3834 , G06F9/3838
摘要： A vector data access unit includes data access ordering circuitry, for issuing data access requests indicated by elements of earlier and a later vector instructions, one being a write instruction. An element indicating the next data access for each of the instructions is determined. The next data accesses for the earlier and the later instructions may be reordered. The next data access of the earlier instruction is selected if the position of the earlier instruction's next data element is less than or equal to the position of the later instruction's next data element minus a predetermined value. The next data access of the later instruction may be selected if the position of the earlier instruction's next data element is higher than the position of the later instruction's next data element minus a predetermined value. Thus data accesses from earlier and later instructions are partially interleaved.

8. 发明授权

US09557995B2 Data processing apparatus and method for performing segmented operations 有权
标题翻译：用于执行分段操作的数据处理装置和方法
公开(公告)号：US09557995B2
公开(公告)日：2017-01-31
申请号：US14175268
申请日：2014-02-07
申请人： ARM LIMITED
发明人： Mbou Eyole-Monono , Alastair David Reid , Matthias Lothar Böttcher , Giacomo Gabrielli
IPC分类号： G06F9/00 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30036 , G06F9/30014 , G06F9/30072 , G06F9/30076 , G06F9/30098 , G06F9/3887 , G06F9/3891
摘要： A data processing apparatus and method are provided for performing segmented operations. The data processing apparatus comprises a vector register store for storing vector operands, and vector processing circuitry providing N lanes of parallel processing, and arranged to perform a segmented operation on up to N data elements provided by a specified vector operand, each data element being allocated to one of the N lanes. The up to N data elements forms a plurality of segments, and performance of the segmented operation comprises performing a separate operation on the data elements of each segment, the separate operation involving interaction between the lanes containing the data elements of the associated segment. Predicate generation circuitry is responsive to a compute descriptor instruction specifying an input vector operand comprising a plurality of segment descriptors, to generate per lane predicate information used by the vector processing circuitry when performing the segmented operation to maintain a boundary between each of the plurality of segments. As a result, interaction between lanes containing data elements from different segments is prevented. This allows very effective utilisation of the lanes of parallel processing within the vector processing circuitry to be achieved.
摘要翻译：提供了一种用于执行分段操作的数据处理装置和方法。数据处理装置包括用于存储向量操作数的向量寄存器存储器和提供N个并行处理通道的向量处理电路，并且被布置为对由指定向量操作数提供的多达N个数据元素执行分段操作，每个数据元素被分配到N条车道之一。最多N个数据元素形成多个段，并且分段操作的执行包括对每个段的数据元素执行单独的操作，该单独操作涉及包含相关段的数据元素的通道之间的交互。谓词生成电路响应于指定包括多个段描述符的输入向量操作数的计算描述符指令，以在执行分割操作时生成由向量处理电路使用的每通道谓词信息，以维持多个段中的每个段之间的边界。结果，阻止了包含来自不同段的数据元素的通道之间的相互作用。这允许在矢量处理电路内非常有效地利用并行处理的通道。

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