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1. 发明申请

US20110012766A1 MULTI-BIT SIGMA-DELTA MODULATOR WITH REDUCED NUMBER OF BITS IN FEEDBACK PATH 有权
标题翻译：在反馈路径中具有减少位数的多位SIGMA-DELTA调制器
公开(公告)号：US20110012766A1
公开(公告)日：2011-01-20
申请号：US12819096
申请日：2010-06-18
申请人： Robert Henrikus Margaretha Van Veldhoven
发明人： Robert Henrikus Margaretha Van Veldhoven
IPC分类号： H03M3/00 , H03K7/02
CPC分类号： H03M3/428 , H03M3/452 , H03M7/302
摘要： A sigma-delta modulator for an ADC, passes an input signal to a loop filter, then to a multi-bit quantizer of the modulator. An output of the quantizer is passed to a digital filter, and a feedback signal is passed back to the loop filter, the feedback signal having fewer bits than are produced by the multi-bit quantizer. The digital filter has an order greater than one in the passband of the sigma-delta modulator.
摘要翻译：用于ADC的Σ-Δ调制器将输入信号传递到环路滤波器，然后传送到调制器的多位量化器。量化器的输出被传递到数字滤波器，并且反馈信号被传回到环路滤波器，反馈信号具有比由多位量化器产生的位少的位。数字滤波器在Σ-Δ调制器的通带中具有大于1的阶数。

2. 发明授权

US07113119B2 Electronic circuit with a sigma delta A/D converter 有权
标题翻译：具有Σ-ΔA/ D转换器的电子电路
公开(公告)号：US07113119B2
公开(公告)日：2006-09-26
申请号：US10502728
申请日：2002-12-23
申请人： Robert Henrikus Margaretha Van Veldhoven , Lucien Johannes Breems , Eise Carel Dijkmans
发明人： Robert Henrikus Margaretha Van Veldhoven , Lucien Johannes Breems , Eise Carel Dijkmans
IPC分类号： H03M3/00
CPC分类号： H03M3/348 , H03M3/424
摘要： The A/D convener has a digital output for outputting a digital output signal selected from a set of three or more available values. A feedback loop generates the digital output signal so that a time averaged difference between an analog input signal and an analog feedback signal representative of the digital output signal is minimized. A feedback signal generator generates successive signal levels of the feedback signal. A return to zero switch inserts predetermined return to zero levels between the signal levels in the feedback signal. The return to zero switch is also used to provide the signal level for one of the available values.
摘要翻译： A / D转换器具有用于输出从一组三个或更多个可用值中选择的数字输出信号的数字输出。反馈回路产生数字输出信号，使得模拟输入信号和表示数字输出信号的模拟反馈信号之间的时间平均差最小化。反馈信号发生器产生反馈信号的连续信号电平。返回到零开关将反馈信号中的信号电平之间的预定值恢复为零电平。返回零开关也用于为可用值之一提供信号电平。

3. 发明申请

US20080218392A1 Signal Receiver and Mobile Communication Device 失效
标题翻译：信号接收机和移动通信设备
公开(公告)号：US20080218392A1
公开(公告)日：2008-09-11
申请号：US11577499
申请日：2005-10-11
申请人： Robert Henrikus Margaretha Van Veldhoven , Lucien Johannes Breems
发明人： Robert Henrikus Margaretha Van Veldhoven , Lucien Johannes Breems
IPC分类号： H04M3/04 , H03M3/00
CPC分类号： H03M3/394 , H03M3/424 , H03M3/452 , H03M3/462
摘要： A signal receiver processing circuit is for isolating a desired signal from analog input signal that is susceptible to variations in signal power, e.g. from a radio front end (12). The device has a variable gain amplifier (13) and an analog to digital converter (14) for providing a digital signal to a digital signal processor (15), the digital signal processor including a digital filter. The device has a control unit (16) for adjusting a filtering accuracy of the analog to digital converter (14) and/or the digital signal processor unit (15) in dependence of a signal quality of the input signal.
摘要翻译：信号接收机处理电路用于将期望的信号与容易受信号功率变化影响的模拟输入信号进行隔离。从无线电前端（12）。该装置具有可变增益放大器（13）和用于向数字信号处理器（15）提供数字信号的模数转换器（14），数字信号处理器包括数字滤波器。该装置具有控制单元（16），用于根据输入信号的信号质量来调节模数转换器（14）和/或数字信号处理器单元（15）的滤波精度。

4. 发明申请

US20080191914A1 Signal Strength Indicator 有权
标题翻译：信号强度指示器
公开(公告)号：US20080191914A1
公开(公告)日：2008-08-14
申请号：US11910451
申请日：2006-03-28
申请人： Robert Henrikus Margaretha Van Veldhoven
发明人： Robert Henrikus Margaretha Van Veldhoven
IPC分类号： H03M1/00
CPC分类号： H03M3/362 , H03M3/424 , H03M3/486 , H03M3/49
摘要： A device is for digitally processing an input signal that is susceptible to variations in signal strength. The signal (48) is analog to digital converted into a bitstream signal (47), the bitstream signal representing the input signal by consecutive digital values. The device has a signal strength detection circuit (32) for generating a control signal indicative for an overload condition in which the signal strength exceeds a input range of the analog to digital converter, e.g. a sigma-delta modulator The signal strength detection circuit detects, in the bitstream signal, a sequence (49,50) of adjacent and equal digital values, the sequence having at least a predetermined length. The circuit detects the overload condition effectively and fast, avoiding the delay of signal strength detection in a digital processor.
摘要翻译：一种设备用于数字处理易受信号强度变化影响的输入信号。信号（48）被模拟数字转换成比特流信号（47），比特流信号通过连续的数字值表示输入信号。该装置具有信号强度检测电路（32），用于产生指示过载状态的控制信号，其中信号强度超过模数转换器的输入范围，例如， Σ-Δ调制器信号强度检测电路在比特流信号中检测相邻和相等数字值的序列（49,50），该序列具有至少预定长度。该电路有效且快速地检测过载状况，避免了数字处理器中信号强度检测的延迟。

5. 发明申请

US20120274495A1 MULTI-BIT SIGMA-DELTA MODULATOR WITH REDUCED NUMBER OF BITS IN FEEDBACK PATH 审中-公开
标题翻译：在反馈路径中具有减少位数的多位SIGMA-DELTA调制器
公开(公告)号：US20120274495A1
公开(公告)日：2012-11-01
申请号：US13548069
申请日：2012-07-12
申请人： Robert Henrikus Margaretha Van Veldhoven
发明人： Robert Henrikus Margaretha Van Veldhoven
IPC分类号： H03M3/02
CPC分类号： H03M3/428 , H03M3/452 , H03M7/302
摘要： A sigma-delta modulator for an ADC, passes an input signal to a loop filter, then to a multi-bit quantizer of the modulator. An output of the quantizer is passed to a digital filter, and a feedback signal is passed back to the loop filter, the feedback signal having fewer bits than are produced by the multi-bit quantizer. The digital filter has an order greater than one in the passband of the sigma-delta modulator.
摘要翻译：用于ADC的Σ-Δ调制器将输入信号传递到环路滤波器，然后传送到调制器的多位量化器。量化器的输出被传递到数字滤波器，并且反馈信号被传回到环路滤波器，反馈信号具有比由多位量化器产生的位少的位。数字滤波器在Σ-Δ调制器的通带中具有大于1的阶数。

6. 发明授权

US07042378B2 Circuit with a digital to analog converter 有权
标题翻译：电路与数模转换器
公开(公告)号：US07042378B2
公开(公告)日：2006-05-09
申请号：US10503048
申请日：2002-01-23
申请人： Robert Henrikus Margaretha Van Veldhoven
发明人： Robert Henrikus Margaretha Van Veldhoven
IPC分类号： H03M1/66
CPC分类号： H03M3/464 , H03M3/424
摘要： A first and second signal source are coupled to an analog output in a digital input signal dependent configuration. The signal sources so that a contribution of their source signals adds up in a first or a second direction when the digital input assumes a first or a second value respectively. The source signals counteract each other when the digital input signal assumes a third value. The signs with which the source signals contribute to the analog signal level for the third value are alternated, so that both signs occur substantially equally frequently for each of the signal sources. The spectral density of a deviation signal due to said alternating is concentrated at high frequencies. In an embodiment the spectral density is moved to high frequency by modulating the alternation onto a high frequency alternation that is used to generate return to zero levels between digital input signal dependent levels.
摘要翻译：第一和第二信号源以数字输入信号依赖配置耦合到模拟输出。信号源使得当数字输入分别采用第一或第二值时，它们的源信号的贡献在第一或第二方向上相加。当数字输入信号呈现第三值时，源信号相互抵消。源信号对第三值的模拟信号电平有贡献的符号是交替的，因此对于每个信号源，这两个符号基本上同样频繁出现。由于所述交替的偏差信号的频谱密度集中在高频。在一个实施例中，通过将交变调制到用于在数字输入信号相关电平之间产生返回到零电平的高频交变上，将频谱密度移动到高频。

7. 发明授权

US07564396B2 Signal receiver and mobile communication device for isolating a desired signal that is susceptible to variations in signal power 失效
标题翻译：用于隔离易受信号功率变化影响的期望信号的信号接收器和移动通信装置
公开(公告)号：US07564396B2
公开(公告)日：2009-07-21
申请号：US11577499
申请日：2005-10-11
申请人： Robert Henrikus Margaretha Van Veldhoven , Lucien Johannes Breems
发明人： Robert Henrikus Margaretha Van Veldhoven , Lucien Johannes Breems
IPC分类号： H03M1/38
CPC分类号： H03M3/394 , H03M3/424 , H03M3/452 , H03M3/462
摘要： A signal receiver processing circuit for isolating a desired signal from an analog input signal that is susceptible to variations in signal power, e.g. from a radio front end, includes a variable gain amplifier, an analog to digital converter, a digital signal processor, and a control unit. The analog to digital converter provides a digital signal to the digital signal processor. The digital signal processor includes a digital filter. The control unit adjusts a filtering accuracy of the analog to digital converter and/or the digital signal processor unit in dependence of a signal quality of the input signal.
摘要翻译：信号接收机处理电路，用于将期望的信号与容易受信号功率变化影响的模拟输入信号进行隔离。从无线电前端包括可变增益放大器，模数转换器，数字信号处理器和控制单元。模数转换器向数字信号处理器提供数字信号。数字信号处理器包括数字滤波器。控制单元根据输入信号的信号质量调整模数转换器和/或数字信号处理器单元的滤波精度。

8. 发明申请

US20080117087A1 Signal Strength Indicator 有权
标题翻译：信号强度指示器
公开(公告)号：US20080117087A1
公开(公告)日：2008-05-22
申请号：US11577500
申请日：2005-10-11
申请人： Robert Henrikus Margaretha Van Veldhoven
发明人： Robert Henrikus Margaretha Van Veldhoven
IPC分类号： H03M1/00
CPC分类号： H03M3/394 , H03M3/424 , H03M3/452 , H03M3/462
摘要： A signal processing circuit has an analog to digital converter (31) for providing a digital signal to a processor (15) from an analog input signal that is susceptible to variations in signal power, e.g. from a radio front end (12). The device has a variable gain amplifier (13) controlled by a gain control signal based on detected signal strength. The analog to digital converter has a loop comprising a loop filter for processing the input signal. A signal strength detection circuit (32) is provided for generating the gain control signal, which signal strength detection circuit has loop signal detector for detecting the signal strength from the loop. Hence a received signal strength indicator RSSI is directly coupled to the analog to digital converter (31), avoiding the delay of signal strength detection in the digital processor.
摘要翻译：信号处理电路具有模数转换器（31），用于从容易受信号功率变化影响的模拟输入信号（15）提供数字信号给处理器（15）。从无线电前端（12）。该装置具有基于检测到的信号强度由增益控制信号控制的可变增益放大器（13）。模数转换器具有包括用于处理输入信号的环路滤波器的回路。提供信号强度检测电路（32），用于产生增益控制信号，该信号强度检测电路具有环路信号检测器，用于检测来自环路的信号强度。因此，接收的信号强度指示器RSSI直接耦合到模数转换器（31），避免了数字处理器中信号强度检测的延迟。

9. 发明授权

US07236594B2 Random generator description 失效
标题翻译：随机发生器描述
公开(公告)号：US07236594B2
公开(公告)日：2007-06-26
申请号：US10188139
申请日：2002-07-02
申请人： Robert Henrikus Margaretha Van Veldhoven , Gian Hoogzaad
发明人： Robert Henrikus Margaretha Van Veldhoven , Gian Hoogzaad
IPC分类号： H04L9/00
CPC分类号： H03K3/84
摘要： A pseudo random generator comprising a shift register comprising a first flip flop (F0) and n further flip-flops (F1 . . . Fn) each flip-flop (F0) having a D input, a non-inverting output, an inverting output, and a common clock (fclk) input and the first flip-flop (F0) having a set input, each of the non-inverting outputs being connected via a NOR gate (10) to the set input of the first flip-flop (F0) and each of the non-inverting outputs of the flip-flops (F0 . . . Fn) being connected to the input of the first flip-flop (F0) via an XOR gate (11), characterised in that the generator comprises at least one additional logic gate (13, 14, 15; 17, 18, 19) including at least one additional flip-flop (14;18).The extra logic gates may comprise gated to toggle between the inverting end and the non-inverting outputs, or to generate an extra ‘0’ at the output or to chop, preferably randomly, the input signal.
摘要翻译：一种伪随机生成器，包括：移位寄存器，包括具有D输入的每个触发器（F 0）和非反相输出的第一触发器（F0）和n个另外的触发器（F 1 ... Fn）反相输出和公共时钟（fclk）输入和具有设定输入的第一触发器（F0），每个非反相输出端经由或非门（10）连接到第一触发器（F 0）和触发器的每个非反相输出（F0 ... Fn）经由异或门（11）连接到第一触发器（F 0）的输入端，其特征在于，所述发生器包括至少一个包括至少一个附加触发器（14; 18）的附加逻辑门（13,14,15,17,18,19）。额外的逻辑门可以包括门控以在反相端和非反相输出之间切换，或者在输出处产生额外的“0”或者优选地随机输入输入信号。

10. 发明授权

US09007247B2 Multi-bit sigma-delta modulator with reduced number of bits in feedback path 有权
标题翻译：反馈路径中位数减少的多位Σ-Δ调制器
公开(公告)号：US09007247B2
公开(公告)日：2015-04-14
申请号：US13548069
申请日：2012-07-12
申请人： Robert Henrikus Margaretha Van Veldhoven
发明人： Robert Henrikus Margaretha Van Veldhoven
IPC分类号： H03M3/02 , H03M7/30 , H03M3/00
CPC分类号： H03M3/428 , H03M3/452 , H03M7/302
摘要： A sigma-delta modulator for an ADC, passes an input signal to a loop filter, then to a multi-bit quantizer of the modulator. An output of the quantizer is passed to a digital filter, and a feedback signal is passed back to the loop filter, the feedback signal having fewer bits than are produced by the multi-bit quantizer. The digital filter has an order greater than one in the passband of the sigma-delta modulator.
摘要翻译：用于ADC的Σ-Δ调制器将输入信号传递到环路滤波器，然后传送到调制器的多位量化器。量化器的输出被传递到数字滤波器，并且反馈信号被传回到环路滤波器，反馈信号具有比由多位量化器产生的位少的位。数字滤波器在Σ-Δ调制器的通带中具有大于1的阶数。

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