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1. 发明授权

US11689213B2 Architecture for analog multiplier-accumulator with binary weighted charge transfer capacitors 有权
公开(公告)号：US11689213B2
公开(公告)日：2023-06-27
申请号：US17334782
申请日：2021-05-30
申请人： Ceremorphic, Inc.
发明人： Martin Kraemer , Ryan Boesch , Wei Xiong
IPC分类号： H03M3/00 , H03M3/04 , G06J1/00 , H03M1/38 , H03K19/20
CPC分类号： H03M3/04 , G06J1/00 , H03M1/38 , H03K19/20
摘要： An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspect of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor to form an analog multiplication product as a charge applied to the differential charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.

2. 发明申请

US20180309460A1 POWER-EFFICIENT FLASH QUANTIZER FOR DELTA SIGMA CONVERTER 审中-公开
公开(公告)号：US20180309460A1
公开(公告)日：2018-10-25
申请号：US15914833
申请日：2018-03-07
申请人： Abhishek Bandyopadhyay , Daniel Peter Canniff , Mariana Tosheva Markova , Edward Chapin Guthrie
发明人： Abhishek Bandyopadhyay , Daniel Peter Canniff , Mariana Tosheva Markova , Edward Chapin Guthrie
IPC分类号： H03M3/00 , H03M1/06 , H03M1/36 , H03M3/02 , H03M3/04
CPC分类号： H03M3/424 , H03M1/002 , H03M1/066 , H03M1/361 , H03M1/365 , H03M3/02 , H03M3/04 , H03M3/32 , H03M3/452 , H03M3/464
摘要： A multibit flash quantizer circuit, such as included as a portion of delta-sigma conversion circuit, can be operated in a dynamic or configurable manner. Information indicative of at least one of an ADC input slew rate or a prior quantizer output code can be used to establish a flash quantizer conversion window. Within the selected conversion window, comparators in the quantizer circuit can be made active. Comparators outside the conversion window can be made dormant, such as depowered or biased to save power. An output from such dormant converters can be preloaded and latched. In this manner, full resolution is available without requiring that all comparator circuits within the quantizer remain active at all times.

3. 发明授权

US4071842A Apparatus for analog to digital conversion 失效
标题翻译：用于模数转换的装置
公开(公告)号：US4071842A
公开(公告)日：1978-01-31
申请号：US756399
申请日：1977-01-03
申请人： Stuart Keene Tewksbury
发明人： Stuart Keene Tewksbury
IPC分类号： H03M3/02 , G06T9/00 , H03M3/04 , H04B14/06 , H03K13/22
CPC分类号： H03M3/04 , G06T9/004
摘要： An input analog signal is converted to a digital output signal by an oversampled predictive DPCM coder which includes an n stage delay line in the feedback loop. The n delay line outputs are weighted by coefficients a.sub.i . . . a.sub.n selected according to the relationship ##EQU1## AND THEN SUMMED. Alternatively, the feedback loop may comprise a chain of n integrators arranged so that the signal fed back to the comparator is the sum of single, double, triple...n order integration. By so doing, the coder attenuates the signal power at the quantizer input while the attenuator coefficients are independent of the input signal statistics.A similar technique may also be applied in an oversampled error feedback coder, which includes a feedback loop having an n stage delay line. Here again, the delay line outputs are weighted in accordance with the above relationship. Alternatively, a chain of n integrators may be used in the coder input, and an identical chain employed in the feedback loop. By so doing, the coder attenuates the coding noise power in the signal band while the coder design is rendered independent of the quantizing error statistics.
摘要翻译：输入模拟信号由过采样的预测DPCM编码器转换为数字输出信号，该编码器在反馈回路中包括n级延迟线。 n个延迟线输出由系数ai加权。。。根据的关系选择

4. 发明授权

US3921204A Digital encoding system 失效
标题翻译：数字编码系统
公开(公告)号：US3921204A
公开(公告)日：1975-11-18
申请号：US28180772
申请日：1972-08-18
申请人： POST OFFICE
发明人： THOMPSON JOHN EDWARD
IPC分类号： H03M3/02 , H03M3/04 , H04N7/32 , H04N11/04 , H04N5/40 , H04N9/40
CPC分类号： H04N11/046 , H03M3/04
摘要： Methods of encoding in digital form an analogue signal including a modulated sub-carrier wave, such as a colour television video signal, are described in which the rate of sampling of the analogue signal is a simple factor, for example 3, times the frequency of the sub-carrier wave. The methods of encoding include comparing the instantaneous value of the analogue signal with a previously occurring value, which conveniently is spaced by one or more cycles of the sub-carrier from the instantaneous value, and then encoding the difference between the two values. From an N.T.S.C. signal the spacing between the two values may be one cycle of the sub-carrier wave, or about one line of the scan, (the actual spacing being an integral number of cycles of the sub-carrier wave, or both differences can be combined to produce a diagonal difference signal. The same spacings can be used for a PAL signal if a PAL modifier is used, otherwise a vertical spacing of two lines is necessary because of the change of phase of the sub-carrier in alternate lines. The differences from several spacings can be combined trigonometrically to synthesise a difference corresponding to a desired spacing, such as one cycle of the sub-carrier wave.

5. 发明授权

US3825831A Differential pulse code modulation apparatus 失效
标题翻译：差分脉冲代码调制装置
公开(公告)号：US3825831A
公开(公告)日：1974-07-23
申请号：US19219871
申请日：1971-10-26
申请人： NIPPON ELECTRIC CO
发明人： ISHIGURO T
IPC分类号： H03M7/32 , H03M3/02 , H03M3/04 , H03M7/00 , H04B1/00 , H04B7/00
CPC分类号： H03M3/04 , H03M3/02
摘要： A differential pulse code modulator includes a delta modulator for converting an analog input signal to a delta modulated signal, a digital filter for removing quantizing noise components, and a direct feedback pulse code modulation encoder. The feedback encoder includes a subtractor for determining the difference between a decoded digital signal and the output of the digital filter, a digital integrator for integrating the output of the subtractor, a digital coder for converting the output of the integrator to a differential pulse code modulation signal and a digital decoder for converting the differential signal to the decoded digital signal supplied to the subtractor. Clock pulses are supplied to the delta modulator, the digital filter, and the direct feedback pulse code modulation encoder.
摘要翻译：差分脉冲编码调制器包括用于将模拟输入信号转换为增量调制信号的增量调制器，用于去除量化噪声分量的数字滤波器和直接反馈脉冲编码调制编码器。反馈编码器包括用于确定解码数字信号和数字滤波器的输出之间的差的减法器，用于对减法器的输出进行积分的数字积分器，用于将积分器的输出转换为差分脉冲编码调制的数字编码器信号和数字解码器，用于将差分信号转换为提供给减法器的解码数字信号。时钟脉冲被提供给增量调制器，数字滤波器和直接反馈脉冲编码调制编码器。

6. 发明授权

US3251052A Reversible analog to digital converter 失效
标题翻译：可逆模数转换器
公开(公告)号：US3251052A
公开(公告)日：1966-05-10
申请号：US28062463
申请日：1963-05-15
申请人： TOWSON LAB INC
发明人： HOFFMAN PHILIP A , EGERTON JR MCKENNY W
IPC分类号： G06G7/06 , H03M1/00 , H03M3/04
CPC分类号： H03M1/464 , G06G7/06 , H03M1/02 , H03M1/1225 , H03M1/466 , H03M1/804 , H03M3/04

7. 发明授权

US3127601A Analog-to-digital converter 失效
公开(公告)号：US3127601A
公开(公告)日：1964-03-31
申请号：US6651260
申请日：1960-11-01
申请人： BELL TELEPHONE LABOR INC
发明人： KAENEL REGINALD A
IPC分类号： H03M1/00 , H03M3/04
CPC分类号： H03M1/48 , H03M3/04

8. 发明授权

US3071727A Bandwidth reduction system 失效
标题翻译：带宽减少系统
公开(公告)号：US3071727A
公开(公告)日：1963-01-01
申请号：US10848261
申请日：1961-05-08
申请人： BELL TELEPHONE LABOR INC
发明人： KITSOPOULOS SOTIRIOS C
IPC分类号： H03M1/00 , H03M3/04 , H04B1/66 , H04N7/26
CPC分类号： H03M1/005 , H03M1/12 , H03M3/04 , H04B1/66 , H04N19/30 , H04N19/90

9. 发明授权

US2681385A Reduction of signal redundancy 失效
标题翻译：减少信号冗余
公开(公告)号：US2681385A
公开(公告)日：1954-06-15
申请号：US17097750
申请日：1950-06-29
申请人： BELL TELEPHONE LABOR INC
发明人： OLIVER BERNARD M
IPC分类号： H03M3/04 , H04L25/48
CPC分类号： H03M3/04

10. 发明授权

US4296412A Method and apparatus for signal transmission 失效
标题翻译：用于信号传输的方法和装置
公开(公告)号：US4296412A
公开(公告)日：1981-10-20
申请号：US92520
申请日：1979-11-08
申请人： Jiri Mastner
发明人： Jiri Mastner
IPC分类号： G01R15/22 , G01R15/26 , H03M3/04 , H04B10/00 , G08C19/16 , G08C25/00
CPC分类号： G01R15/26 , G01R15/22 , H03M3/04 , H04B10/00
摘要： Differential pulse code modulation (DPCM) is used for a fast digital transmission of the analog input signal. In the DPCM modulator, a difference is built between the scaled input signal and the output of a digital/analog converter, which is controlled by a digital integrator. Comparator means generate a DPCM signal with values corresponding to "no change", "up-" or "down-integration" in dependence on the amplitude and polarity of the mentioned difference. The zero-crossings of the input signal itself are detected separately and are converted into a one-bit PCM signal, having the value "reset". The DPCM and PCM signals are combined into a multi-value control signal, which is fed to the integrator and causes it to follow-up the input signal and make a reset at each zero-crossing. The multi-value control signal is coded, transmitted to the receiver side of the link and decoded. The different decoded values control an integrator in the demodulator in the same way, as in the modulator. The input signal is reconstructed by digital integration of the DPCM. The periodical reset of the receiving integrator avoids a dc offset of its output, caused in any conventional DPCM system by the initial conditions of the integrator, by transmission errors, by an offset of the modulator and so forth.
摘要翻译：差分脉冲编码调制（DPCM）用于模拟输入信号的快速数字传输。在DPCM调制器中，缩放的输入信号和数字/模拟转换器的输出之间建立了差异，数字/模拟转换器由数字积分器控制。比较器意味着根据所提到的差的振幅和极性产生具有对应于“不变”，“上”或“下积分”的值的DPCM信号。单独检测输入信号本身的过零点，并将其转换为具有值“复位”的1位PCM信号。 DPCM和PCM信号被组合成多值控制信号，其被馈送到积分器并使其跟随输入信号并在每个过零点进行复位。多值控制信号被编码，发送到链路的接收机侧并进行解码。不同的解码值以与调制器相同的方式控制解调器中的积分器。通过DPCM的数字积分重建输入信号。接收积分器的周期性复位避免了在任何常规DPCM系统中由积分器的初始条件，传输误差，调制器偏移等引起的输出的直流偏移。

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