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1. 发明授权

US08594217B2 Parallel implementation of maximum a posteriori probability decoder 有权
标题翻译：并行实现最大后验概率解码器
公开(公告)号：US08594217B2
公开(公告)日：2013-11-26
申请号：US13312615
申请日：2011-12-06
申请人： Brian Fanous , Halldor N. Stefansson
发明人： Brian Fanous , Halldor N. Stefansson
IPC分类号： H04L5/12
CPC分类号： G06F17/16 , H03M13/3905 , H03M13/3922 , H03M13/3927 , H03M13/3966 , H03M13/616
摘要： A MAP decoder may be implemented in parallel. In one implementation, a device may receive an input array that represents received encoded data and calculate, in parallel, a series of transition matrices from the input array. The device may further calculate, in parallel, products of the cumulative products of the series of transition matrices and an initialization vector. The device may further calculate, in parallel and based on the products of the cumulative products of the series of transition matrices and the initialization vector, an output array that corresponds to a decoded version of the received encoded data in the input array.
摘要翻译：可以并行地实现MAP解码器。在一个实现中，设备可以接收表示接收的编码数据的输入阵列，并且平行地计算来自输入阵列的一系列转移矩阵。该装置还可以并行地计算一系列转移矩阵的累积乘积和初始化向量的乘积。该装置可以并行地并且基于一系列转移矩阵和初始化向量的累积乘积的乘积进一步计算与输入阵列中接收到的编码数据的解码版本相对应的输出阵列。

2. 发明申请

US20090089648A1 LOW POWER VITERBI DECODER USING SCARCE STATE TRANSITION AND PATH PRUNING 审中-公开
标题翻译：低功率VITERBI解码器使用SCARCE状态转换和路径调整
公开(公告)号：US20090089648A1
公开(公告)日：2009-04-02
申请号：US11865643
申请日：2007-10-01
申请人： Chi Ying Tsui , Jie Jin
发明人： Chi Ying Tsui , Jie Jin
IPC分类号： G06F11/10
CPC分类号： H03M13/41 , H03M13/3776 , H03M13/3955 , H03M13/3966
摘要： Low power Viterbi decoder techniques using Scarce State Transition (SST) and path pruning and related methods and systems are provided, which facilitate practical implementations that reduce the computational overhead and power consumption. In addition, the invention provides uneven-partitioned memory architectures for the survivor memory unit that advantageously exploits the characteristic of the maximum likelihood state probability distribution of the SST decoder facilitating further power reduction. The disclosed details enable various refinements and modifications according to decoder and system design considerations.
摘要翻译：提供了使用Scarce状态转换（SST）和路径修剪及相关方法和系统的低功耗维特比解码技术，这有助于减少计算开销和功耗的实际实现。此外，本发明为幸存者存储器单元提供了不均匀分配的存储器体系结构，其有利地利用了SST解码器的最大似然状态概率分布的特性，便于进一步的功率降低。所公开的细节可以根据解码器和系统设计考虑进行各种改进和修改。

3. 发明申请

US20020021770A1 Reduced-latency soft-in/soft-out module 审中-公开
标题翻译：降低延迟软启/退出模块
公开(公告)号：US20020021770A1
公开(公告)日：2002-02-21
申请号：US09848778
申请日：2001-05-03
发明人： Peter A. Beerel , Keith M. Chugg , Georgios D. Dimou , Phunsak Thiennviboon
IPC分类号： H03D001/00 , H04L027/06
CPC分类号： H03M13/3905 , H03M13/2957 , H03M13/3966 , H03M13/6572
摘要： Decoding an encoded signal (for example, a turbo encoded signal, a block encoded signal or the like) is performed by demodulating the received encoded signal to produce soft information, and iteratively processing the soft information with one or more soft-in/soft-output (SISO) modules. At least one of the SISO modules uses a tree structure to compute forward and backward state metrics. More generally, iterative detection is performed by receiving an input signal corresponding to one or more outputs of a module whose soft-inverse can be computed by running the forward-backward algorithm on a trellis representation of the module, and determining the soft inverse of the module by computing forward and backward state metrics of the received input signal using a tree structure.
摘要翻译：通过解调接收到的编码信号以产生软信息来对编码信号（例如，turbo编码信号，块编码信号等）进行解码，并且利用一个或多个软/软编码信号迭代地处理软信息，输出（SISO）模块。至少有一个SISO模块使用树结构来计算前向和后向状态度量。更一般地，通过接收与模块的一个或多个输出相对应的输入信号来执行迭代检测，该模块的软反转可以通过在模块的网格表示上运行前向后向算法来计算，并且确定模块，通过使用树结构计算所接收的输入信号的前向和后向状态度量。

4. 发明授权

US09348798B2 Parallel implementation of maximum a posteriori probability decoder 有权
公开(公告)号：US09348798B2
公开(公告)日：2016-05-24
申请号：US14057132
申请日：2013-10-18
申请人： The MathWorks, Inc.
发明人： Brian J. Fanous , Halldor N. Stefansson
IPC分类号： H04L27/06 , G06F17/16 , H03M13/39 , H03M13/00
CPC分类号： G06F17/16 , H03M13/3905 , H03M13/3922 , H03M13/3927 , H03M13/3966 , H03M13/616
摘要： A MAP decoder may be implemented in parallel. In one implementation, a device may receive an input array that represents received encoded data and calculate, in parallel, a series of transition matrices from the input array. The device may further calculate, in parallel, products of the cumulative products of the series of transition matrices and an initialization vector. The device may further calculate, in parallel and based on the products of the cumulative products of the series of transition matrices and the initialization vector, an output array that corresponds to a decoded version of the received encoded data in the input array.

5. 发明授权

US07870176B2 Method of and apparatus for implementing fast orthogonal transforms of variable size 有权
标题翻译：用于实现可变大小的快速正交变换的方法和装置
公开(公告)号：US07870176B2
公开(公告)日：2011-01-11
申请号：US11176149
申请日：2005-07-07
申请人： Doron Solomon , Gilad Garon
发明人： Doron Solomon , Gilad Garon
IPC分类号： G06F17/14
CPC分类号： H03M13/4169 , G06F17/142 , H03M13/1105 , H03M13/2957 , H03M13/39 , H03M13/3966 , H03M13/41 , H03M13/4107 , H03M13/4146 , H03M13/6508 , H03M13/6511 , H03M13/6513 , H03M13/6516 , H03M13/6561
摘要： A reconfigurable architecture for and method of performing a fast orthogonal transform of vectors in multiple stages, the size of a vector being N, wherein N can vary and the number of stages is a function of N, the architecture comprising: a computational unit configured and arranged so as to include one or more butterfly units; a block including one or more multipliers coupled to the output of the computational unit, configured and arranged so as to perform all of the butterfly computations for at least one stage of the transform; a storage unit configured and arranged so as to store the intermediate results of the butterfly computations and predetermined coefficients for use by the computational unit for performing each butterfly computation, the storage unit including memory and multiplexing architecture; the storage unit including memory and multiplexing architecture; a multiplexer unit configured and arranged so as to time multiplex all of the butterfly computations of the transform using said computation unit for the one stage so that only one computation unit is required for the stage; and a controller configured and arranged so as to provide coefficients to the computational unit, and control the sizes of memory and multiplexing architecture in the storage unit; wherein the multipliers' coefficients, the coefficients of the computational unit, the sizes of memories, and multiplexing architecture, for each stage are modified as a function of the value of N. The architecture can be implemented as an integrated chip, and used in communication devices.
摘要翻译：一种用于执行多级向量的快速正交变换的可重构架构和方法，所述向量的大小为N，其中N可以变化，并且级数是N的函数，所述架构包括：计算单元，其被配置和布置成包括一个或多个蝴蝶单元; 包括耦合到所述计算单元的输出的一个或多个乘法器的块，被配置和布置成为所述变换的至少一个阶段执行所有蝴蝶计算; 存储单元，被配置和布置为存储蝶形计算的中间结果和预定系数，供计算单元用于执行每个蝶式运算，该存储单元包括存储器和复用结构; 所述存储单元包括存储器和复用架构; 多路复用器单元，其被配置和布置为使用所述一级的所述计算单元对所述变换的所有蝶式计算进行时间复用，使得仅需要一个计算单元用于所述级; 以及控制器，其被配置和布置为向所述计算单元提供系数，并且控制所述存储单元中的存储器和复用架构的大小; 其中每个级的乘法器系数，计算单元的系数，存储器的大小和复用架构被修改为N的值的函数。架构可以被实现为集成芯片，并且用于通信设备。

6. 发明授权

US07613990B1 Method and system for a multi-channel add-compare-select unit 有权
标题翻译：多通道加法比较选择单元的方法和系统
公开(公告)号：US07613990B1
公开(公告)日：2009-11-03
申请号：US10717042
申请日：2003-11-18
申请人： William A. Wilkie , David I. Lawrie , Elizabeth R. Cowie
发明人： William A. Wilkie , David I. Lawrie , Elizabeth R. Cowie
IPC分类号： H03M13/00 , G06F11/00 , G01R31/30
CPC分类号： H03M13/3922 , H03M13/3966
摘要： A circuit for a multi-channel add-compare-select unit is disclosed. The circuit includes a compare unit and a datapath. The datapath is coupled to the compare unit, and includes a number of adder units, a selection unit (which is coupled to the adder units), and a number of clocked storage stages.
摘要翻译：公开了一种用于多通道加法比较选择单元的电路。该电路包括比较单元和数据通路。数据路径耦合到比较单元，并且包括多个加法器单元，选择单元（其耦合到加法器单元）和多个计时存储级。

7. 发明授权

US07197691B2 Reduced-latency soft-in/soft-out module 有权
标题翻译：降低延迟软启/退出模块
公开(公告)号：US07197691B2
公开(公告)日：2007-03-27
申请号：US10875979
申请日：2004-06-24
申请人： Peter A. Beerel , Keith M. Chugg , Georgios D. Dimou , Phunsak Thiennviboon
发明人： Peter A. Beerel , Keith M. Chugg , Georgios D. Dimou , Phunsak Thiennviboon
IPC分类号： H03M13/03
CPC分类号： H03M13/3905 , H03M13/2957 , H03M13/3966 , H03M13/6572
摘要： Decoding an encoded signal (for example, a turbo encoded signal, a block encoded signal or the like) is performed by demodulating the received encoded signal to produce soft information, and iteratively processing the soft information with one or more soft-in/soft-output (SISO) modules. At least one of the SISO modules uses a tree structure to compute forward and backward state metrics. More generally, iterative detection is performed by receiving an input signal corresponding to one or more outputs of a module whose soft-inverse can be computed by running the forward-backward algorithm on a trellis representation of the module, and determining the soft inverse of the module by computing forward and backward state metrics of the received input signal using a tree structure.
摘要翻译：通过解调接收到的编码信号以产生软信息来对编码信号（例如，turbo编码信号，块编码信号等）进行解码，并且利用一个或多个软/软编码信号迭代地处理软信息，输出（SISO）模块。至少有一个SISO模块使用树结构来计算前向和后向状态度量。更一般地，通过接收与模块的一个或多个输出相对应的输入信号来执行迭代检测，该模块的软反转可以通过在模块的网格表示上运行前向后向算法来计算，并且确定模块，通过使用树结构计算所接收的输入信号的前向和后向状态度量。

8. 发明授权

US07650561B1 Method of switching from parallel to serial MAP detector 有权
标题翻译：从并行转换到串行MAP检测器的方法
公开(公告)号：US07650561B1
公开(公告)日：2010-01-19
申请号：US11484462
申请日：2006-07-11
申请人： Bengt A. Ulriksson , Richard D. Barndt
发明人： Bengt A. Ulriksson , Richard D. Barndt
IPC分类号： H03M13/03
CPC分类号： H03M13/2957 , H03M13/3707 , H03M13/3905 , H03M13/3966 , H03M13/3972
摘要： A MAP detector system operates in a parallel mode for on-the-fly operations and in a serial mode for error recovery operations. In the parallel mode, a plurality of Viterbi operators process a block of input sampled data in parallel. In the serial mode a selected forward Viterbi operator and two associated reverse Viterbi operators process the entire block of data, in order, to produce soft decision data.
摘要翻译： MAP检测器系统以并行模式操作，用于实时操作和串行模式用于错误恢复操作。在并行模式中，多个维特比运算符并行地处理一组输入采样数据。在串行模式下，选择的前向维特比运算符和两个相关的反向维特比运算符按顺序处理整个数据块，以产生软判决数据。

9. 发明授权

US07263652B2 Maximum likelihood detector and/or decoder 有权
标题翻译：最大似然检测器和/或解码器
公开(公告)号：US07263652B2
公开(公告)日：2007-08-28
申请号：US10867216
申请日：2004-06-14
申请人： Oleg Zaboronski , Andrei Vityaev
发明人： Oleg Zaboronski , Andrei Vityaev
IPC分类号： H03M13/03
CPC分类号： H03M13/6572 , H03M13/395 , H03M13/3966 , H03M13/3972 , H03M13/41 , H03M13/4107
摘要： A maximum likelihood detector receiving a data stream corresponding to ideal values which may include noise, and outputting information specifying a sequence of states of maximum likelihood selected from possible states corresponding to the data stream according to weighting value selections made by the processors, the ideal values being determined by the possible states, including: a pre-processor to obtain first weighting values; processors in a hierarchy, each processor in a select level of the hierarchy is programmed to use, respectively, a plurality of the weighting values to calculate subsequent weighting values indicating respective likelihoods that a section of the data stream values corresponds to each of a plurality of possible state sequences, for each possible initial state and each possible final state, to select further weighting value of highest likelihood corresponding to a state sequence from the initial state to the final state.
摘要翻译：接收对应于可能包括噪声的理想值的数据流的最大似然检测器，并且根据由处理器进行的加权值选择，输出指定从对应于数据流的可能状态中选择的最大似然状态序列的信息，理想值由可能的状态确定，包括：获得第一加权值的预处理器; 层级中的处理器，层次结构的选择级别中的每个处理器被编程为分别使用多个加权值来计算指示相应似然性的后续加权值，即数据流值的一部分对应于多个对于每个可能的初始状态和每个可能的最终状态，可能的状态序列选择对应于从初始状态到最终状态的状态序列的最高似然度的进一步权重值。

10. 发明申请

US20050044474A1 Maximum likelihood detector and/or decoder 有权
标题翻译：最大似然检测器和/或解码器
公开(公告)号：US20050044474A1
公开(公告)日：2005-02-24
申请号：US10867216
申请日：2004-06-14
申请人： Oleg Zaboronski , Andrei Vityaev
发明人： Oleg Zaboronski , Andrei Vityaev
IPC分类号： H03M13/41 , H03M13/03
CPC分类号： H03M13/6572 , H03M13/395 , H03M13/3966 , H03M13/3972 , H03M13/41 , H03M13/4107
摘要： A maximum likelihood detector receiving a data stream corresponding to ideal values which may include noise, and outputting information specifying a sequence of states of maximum likelihood selected from possible states corresponding to the data stream according to weighting value selections made by the processors, the ideal values being determined by the possible states, including: a pre-processor to obtain first weighting values; processors in a hierarchy, each processor in a select level of the hierarchy is programmed to use, respectively, a plurality of the weighting values to calculate subsequent weighting values indicating respective likelihoods that a section of the data stream values corresponds to each of a plurality of possible state sequences, for each possible initial state and each possible final state, to select further weighting value of highest likelihood corresponding to a state sequence from the initial state to the final state.
摘要翻译：接收对应于可能包括噪声的理想值的数据流的最大似然检测器，并且根据由处理器进行的加权值选择，输出指定从对应于数据流的可能状态中选择的最大似然状态序列的信息，理想值由可能的状态确定，包括：获得第一加权值的预处理器; 层级中的处理器，层次结构的选择级别中的每个处理器被编程为分别使用多个加权值来计算指示相应似然性的后续加权值，即数据流值的一部分对应于多个对于每个可能的初始状态和每个可能的最终状态，可能的状态序列选择对应于从初始状态到最终状态的状态序列的最高似然度的进一步权重值。

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