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1. 发明授权

US07197691B2 Reduced-latency soft-in/soft-out module 有权
标题翻译：降低延迟软启/退出模块
公开(公告)号：US07197691B2
公开(公告)日：2007-03-27
申请号：US10875979
申请日：2004-06-24
申请人： Peter A. Beerel , Keith M. Chugg , Georgios D. Dimou , Phunsak Thiennviboon
发明人： Peter A. Beerel , Keith M. Chugg , Georgios D. Dimou , Phunsak Thiennviboon
IPC分类号： H03M13/03
CPC分类号： H03M13/3905 , H03M13/2957 , H03M13/3966 , H03M13/6572
摘要： Decoding an encoded signal (for example, a turbo encoded signal, a block encoded signal or the like) is performed by demodulating the received encoded signal to produce soft information, and iteratively processing the soft information with one or more soft-in/soft-output (SISO) modules. At least one of the SISO modules uses a tree structure to compute forward and backward state metrics. More generally, iterative detection is performed by receiving an input signal corresponding to one or more outputs of a module whose soft-inverse can be computed by running the forward-backward algorithm on a trellis representation of the module, and determining the soft inverse of the module by computing forward and backward state metrics of the received input signal using a tree structure.
摘要翻译：通过解调接收到的编码信号以产生软信息来对编码信号（例如，turbo编码信号，块编码信号等）进行解码，并且利用一个或多个软/软编码信号迭代地处理软信息，输出（SISO）模块。至少有一个SISO模块使用树结构来计算前向和后向状态度量。更一般地，通过接收与模块的一个或多个输出相对应的输入信号来执行迭代检测，该模块的软反转可以通过在模块的网格表示上运行前向后向算法来计算，并且确定模块，通过使用树结构计算所接收的输入信号的前向和后向状态度量。

2. 发明授权

US07761772B2 Using no-refresh DRAM in error correcting code encoder and decoder implementations 有权
标题翻译：使用不刷新DRAM来纠错码编码器和解码器实现
公开(公告)号：US07761772B2
公开(公告)日：2010-07-20
申请号：US11860481
申请日：2007-09-24
申请人： Georgios D. Dimou
发明人： Georgios D. Dimou
IPC分类号： G11C29/00
CPC分类号： G06F11/1044
摘要： Embodiments of the present invention provide Forward Error Correcting Code encoders and decoder structures that use DRAM in their memory designs. DRAM is a very attractive memory options in many electronic systems due to the high memory density provided by DRAM. However, the DRAM is typically not included in ASIC or FPGA implementations of encoders and decoders due to complex refresh requirements of DRAM that are required to maintain data stored in DRAM and may interfere with user access to the memory space during refresh cycles. Embodiments of the present invention provide FECC encoder and decoder structures that are implemented using DRAM that do not require complex refresh operations to be performed on the DRAM to ensure data integrity. Accordingly, embodiments of the present invention maximize memory density without the added complexity of introduced by the refresh requirements of DRAM.
摘要翻译：本发明的实施例提供了在其存储器设计中使用DRAM的前向纠错码编码器和解码器结构。由于DRAM提供的高存储密度，DRAM在许多电子系统中是非常有吸引力的存储器选项。然而，由于DRAM的复杂刷新要求，维护存储在DRAM中的数据所需的DRAM，并且可能在刷新周期期间干扰用户对存储器空间的访问，所以DRAM通常不包括在编码器和解码器的ASIC或FPGA实现中。本发明的实施例提供了使用DRAM实现的FECC编码器和解码器结构，其不需要在DRAM上执行复杂刷新操作以确保数据完整性。因此，本发明的实施例使存储器密度最大化，而不增加由DRAM的刷新要求引入的复杂性。

3. 发明授权

US07743287B2 Using SAM in error correcting code encoder and decoder implementations 有权
标题翻译：使用SAM纠错代码编码器和解码器实现
公开(公告)号：US07743287B2
公开(公告)日：2010-06-22
申请号：US11860490
申请日：2007-09-24
申请人： Georgios D. Dimou
发明人： Georgios D. Dimou
IPC分类号： G11C29/00
CPC分类号： G06F11/1044
摘要： SAM is a very attractive memory option for systems due to its higher speed and reduced area when compared to RAM. However it is generally not used in implementations of FECCs due to its limitation to sequential accesses. According to the present invention, Forward Error Correcting Code encoder and decoder structures are shown to allow the use of SAM in their memory designs. Thus SAM is utilized in FECC implementations to achieve better area efficiency for the same amount of memory as well as higher throughput for the hardware implementations.
摘要翻译：与RAM相比，SAM是一种非常有吸引力的内存选项，因为它具有更高的速度和更小的面积。然而，由于其对顺序访问的限制，它通常不用于FECC的实现。根据本发明，前向纠错码编码器和解码器结构被示出为允许在其存储器设计中使用SAM。因此，SAM用于FECC实现以实现相同量的存储器的更好的面积效率以及用于硬件实现的更高的吞吐量。

4. 发明授权

US07698624B2 Scheduling pipelined state update for high-speed trellis processing 有权
标题翻译：调度高速网格处理的流水线状态更新
公开(公告)号：US07698624B2
公开(公告)日：2010-04-13
申请号：US11396348
申请日：2006-03-31
申请人： Georgios D. Dimou
发明人： Georgios D. Dimou
IPC分类号： H03M13/03
CPC分类号： H03M13/4107 , H03M13/03 , H03M13/2987 , H03M13/3905 , H03M13/3922 , H03M13/41 , H03M13/6502
摘要： Methods, apparatuses, and systems are presented for extracting information from a received signal resulting from a process capable of being represented as a finite state machine having a plurality of states, wherein transitions between the states can be represented by a trellis spanning a plurality of time indices, involving calculating branch metrics taking into account the received signal, calculating state metrics at each time index by taking into account the branch metrics and using a pipelined process, wherein the pipelined process is used to calculate state metrics at a first time index, wherein the pipelined process is then used to calculate state metrics at one or more non-adjacent time indices, and wherein the pipelined process is then used to calculate state metrics at an adjacent time index, and generating at least one output taking into account state metrics for states associated with at least one selected path through the trellis.
摘要翻译：呈现方法，装置和系统，用于从由能够被表示为具有多个状态的有限状态机的处理得到的接收信号中提取信息，其中状态之间的转换可以由跨越多个时间的网格来表示索引，涉及考虑所接收到的信号来计算分支度量，通过考虑分支度量并使用流水线过程来计算每个时间索引处的状态度量，其中流水线过程用于计算第一时间索引处的状态度量，其中流水线过程然后用于计算一个或多个非相邻时间索引处的状态度量，并且其中流水线处理然后用于计算相邻时间索引的状态度量，并且考虑到至少一个输出，考虑到与通过网格的至少一个所选路径相关联的状态。

5. 发明申请

US20080098281A1 USING SAM IN ERROR CORRECTING CODE ENCODER AND DECODER IMPLEMENTATIONS 有权
标题翻译：使用SAM错误修正代码编码器和解码器实现
公开(公告)号：US20080098281A1
公开(公告)日：2008-04-24
申请号：US11860490
申请日：2007-09-24
申请人： Georgios D. Dimou
发明人： Georgios D. Dimou
IPC分类号： G11C29/00
CPC分类号： G06F11/1044
摘要： SAM is a very attractive memory option for systems due to its higher speed and reduced area when compared to RAM. However it is generally not used in implementations of FECCs due to its limitation to sequential accesses. According to the present invention, Forward Error Correcting Code encoder and decoder structures are shown to allow the use of SAM in their memory designs. Thus SAM is utilized in FECC implementations to achieve better area efficiency for the same amount of memory as well as higher throughput for the hardware implementations.
摘要翻译：与RAM相比，SAM是一种非常有吸引力的内存选项，因为它具有更高的速度和更小的面积。然而，由于其对顺序访问的限制，它通常不用于FECC的实现。根据本发明，前向纠错码编码器和解码器结构被示出为允许在其存储器设计中使用SAM。因此，SAM用于FECC实现以实现相同量的存储器的更好的面积效率以及用于硬件实现的更高的吞吐量。

6. 发明申请

US20080098279A1 USING NO-REFRESH DRAM IN ERROR CORRECTING CODE ENCODER AND DECODER IMPLEMENTATIONS 有权
标题翻译：在错误修正代码编码器和解码器实现中使用无刷新DRAM
公开(公告)号：US20080098279A1
公开(公告)日：2008-04-24
申请号：US11860481
申请日：2007-09-24
申请人： Georgios D. Dimou
发明人： Georgios D. Dimou
IPC分类号： G06F11/08
CPC分类号： G06F11/1044
摘要： Embodiments of the present invention provide Forward Error Correcting Code encoders and decoder structures that use DRAM in their memory designs. DRAM is a very attractive memory options in many electronic systems due to the high memory density provided by DRAM. However, the DRAM is typically not included in ASIC or FPGA implementations of encoders and decoders due to complex refresh requirements of DRAM that are required to maintain data stored in DRAM and may interfere with user access to the memory space during refresh cycles. Embodiments of the present invention provide FECC encoder and decoder structures that are implemented using DRAM that do not require complex refresh operations to be performed on the DRAM to ensure data integrity. Accordingly, embodiments of the present invention maximize memory density without the added complexity of introduced by the refresh requirements of DRAM.
摘要翻译：本发明的实施例提供了在其存储器设计中使用DRAM的前向纠错码编码器和解码器结构。由于DRAM提供的高存储密度，DRAM在许多电子系统中是非常有吸引力的存储器选项。然而，由于DRAM的复杂刷新要求，维护存储在DRAM中的数据所需的DRAM，并且可能在刷新周期期间干扰用户对存储器空间的访问，所以DRAM通常不包括在编码器和解码器的ASIC或FPGA实现中。本发明的实施例提供了使用DRAM实现的FECC编码器和解码器结构，其不需要在DRAM上执行复杂刷新操作以确保数据完整性。因此，本发明的实施例使存储器密度最大化，而不增加由DRAM的刷新要求引入的复杂性。

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