专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140115549A1 METHOD FOR VERIFYING DIGITAL TO ANALOG CONVERTER DESIGN 有权
标题翻译：用于验证数字到模拟转换器设计的方法
公开(公告)号：US20140115549A1
公开(公告)日：2014-04-24
申请号：US13965201
申请日：2013-08-13
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Cheng Wang , Chao Liang , Geng Zhong
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H03M1/10 , H03M1/109
摘要： A method for producing a verified design of a digital to analog converter (DAC) starts with providing an HDL representation of the DAC. Numerical values of the analog output signal as a function of the representation of the DAC for a range of numerical values of the digital input signal are simulated with a simulator. A model is used for converting the simulated numerical values of the analog output signal to numerical values of an equivalent model signal in the same digital format as the input signal. A comparator compares the numerical values of the input signal and the model signal and determines differences greater than a defined tolerance.
摘要翻译：用于产生数模转换器（DAC）验证设计的方法从提供DAC的HDL表示开始。使用模拟器模拟模拟输出信号作为数字输入信号数值范围的DAC表示的函数的数值。模型用于将模拟输出信号的模拟数值转换为与输入信号相同的数字格式的等效模型信号的数值。比较器比较输入信号和模型信号的数值，并确定大于定义公差的差值。

2. 发明授权

US09372503B1 Clock signal alignment for system-in-package (SIP) devices 有权
标题翻译：系统级封装（SIP）器件的时钟信号对齐
公开(公告)号：US09372503B1
公开(公告)日：2016-06-21
申请号：US14719549
申请日：2015-05-22
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Gary L. Miller , James G. Gay , Gilford E. Lubbers , Geng Zhong
IPC分类号： G06F1/12 , G06F1/10 , G06F13/16 , G06F17/50 , H03K19/177 , H03K5/135
CPC分类号： G06F1/12 , G06F1/10 , G06F13/1689 , G06F17/5077 , H03K5/135 , H03K19/17736
摘要： A method embodiment of the present disclosure includes receiving a delay value associated with an interconnect delay that is measured across interconnect circuitry communicatively coupling a host semiconductor device with a semiconductor device. The method also includes delaying a local clock signal by an amount of delay indicated by the delay value to produce a delayed local clock signal. The method also includes receiving a delayed source clock signal, where the delayed source clock signal is received from the host semiconductor device via the interconnect circuitry. The method also includes outputting a master clock signal based on a comparison of the delayed source clock signal and the delayed local clock signal, where the master clock signal is utilized to generate one or more aligned clock signals on the semiconductor device that are aligned with a source clock signal generated on the host semiconductor device.
摘要翻译：本公开的方法实施例包括接收与跨主机半导体器件与半导体器件通信耦合的互连电路测量的互连延迟相关联的延迟值。该方法还包括将本地时钟信号延迟由延迟值指示的延迟量，以产生延迟的本地时钟信号。该方法还包括接收延迟的源时钟信号，其中经由互连电路从主机半导体器件接收延迟的源时钟信号。该方法还包括基于延迟的源时钟信号和延迟的本地时钟信号的比较来输出主时钟信号，其中主时钟信号被用于在半导体器件上产生一个或多个对准的时钟信号，该时钟信号与在主机半导体器件上产生的源时钟信号。

3. 发明授权

US08826205B2 Method for verifying digital to analog converter design 有权
标题翻译：数模转换器设计验证方法
公开(公告)号：US08826205B2
公开(公告)日：2014-09-02
申请号：US13965201
申请日：2013-08-13
申请人： Freescale Semiconductor, Inc.
发明人： Cheng Wang , Chao Liang , Geng Zhong
IPC分类号： G06F17/50 , H03M1/10
CPC分类号： G06F17/5036 , H03M1/10 , H03M1/109
摘要： A method for producing a verified design of a digital to analog converter (DAC) starts with providing an HDL representation of the DAC. Numerical values of the analog output signal as a function of the representation of the DAC for a range of numerical values of the digital input signal are simulated with a simulator. A model is used for converting the simulated numerical values of the analog output signal to numerical values of an equivalent model signal in the same digital format as the input signal. A comparator compares the numerical values of the input signal and the model signal and determines differences greater than a defined tolerance.
摘要翻译：用于产生数模转换器（DAC）验证设计的方法从提供DAC的HDL表示开始。使用模拟器模拟模拟输出信号作为数字输入信号数值范围的DAC表示的函数的数值。模型用于将模拟输出信号的模拟数值转换为与输入信号相同的数字格式的等效模型信号的数值。比较器比较输入信号和模型信号的数值，并确定大于定义公差的差值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式