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1. 发明授权

US07148828B2 System and method for timing calibration of time-interleaved data converters 有权
标题翻译：时间交织数据转换器定时校准的系统和方法
公开(公告)号：US07148828B2
公开(公告)日：2006-12-12
申请号：US11120698
申请日：2005-05-03
申请人： Andrew D. Fernandez , Vamsi K. Srikantam , Robert M. R. Neff , Kenneth D. Poulton
发明人： Andrew D. Fernandez , Vamsi K. Srikantam , Robert M. R. Neff , Kenneth D. Poulton
IPC分类号： H03M1/10
CPC分类号： H03M1/10 , H03M1/1205 , H03M1/662
摘要： A method for calibrating time interleaved samplers comprising applying a calibration signal to a time-interleaved sampling device, wherein the signal is coherent with at least one sample clock on the device and is periodic and has a predetermined spectral content and frequency, sampling, by said time-interleaved sampling device, the calibration signal at a plurality of phases to form samples, averaging the formed samples, and calculating the phase error of each sample based on the average calibration signal sample.
摘要翻译：一种用于校准时间交织采样器的方法，包括将校准信号施加到时间交织的采样设备，其中所述信号与所述设备上的至少一个采样时钟相干，并且是周期性的并且具有预定的频谱含量和频率，由所述时间交织采样装置，多个相位的校准信号，以形成样本，对所形成的样本进行平均，以及基于平均校准信号样本计算每个样本的相位误差。

2. 发明授权

US06909310B2 CMOS controlled-impedance transmission line driver 有权
标题翻译： CMOS控制阻抗传输线驱动器
公开(公告)号：US06909310B2
公开(公告)日：2005-06-21
申请号：US10354281
申请日：2003-01-30
申请人： Kenneth D. Poulton , Robert M. R. Neff , Jorge A. Pernillo , Mehrdad Heshami
发明人： Kenneth D. Poulton , Robert M. R. Neff , Jorge A. Pernillo , Mehrdad Heshami
IPC分类号： H03K17/041 , H04L25/02 , H03B1/00
CPC分类号： H04L25/0278 , H03K17/04106 , H04L25/028
摘要： A line driver fabricated from CMOS devices that provides a substantially constant output impedance over a significant range of a time-varying input voltage includes a time-varying current source, a pair of CMOS output loads, and a pair of biasing circuits. Each CMOS output load includes a NMOS transistor and a PMOS transistor connected in parallel and each biased into a linear range of operation. In response to a time-varying input voltage, the time-varying current source draws current from the pair of CMOS output loads in a manner that operates each CMOS output load to collectively establish a time-varying output voltage component at an associated output terminal.
摘要翻译：由CMOS器件制造的线路驱动器，其在时变输入电压的有效范围内提供基本上恒定的输出阻抗，包括时变电流源，一对CMOS输出负载和一对偏置电路。每个CMOS输出负载包括并联连接的NMOS晶体管和PMOS晶体管，并且各自被偏置成线性的操作范围。响应于时变输入电压，随时间变化的电流源以操作每个CMOS输出负载的方式从一对CMOS输出负载中抽取电流，以共同建立相关输出端子处的时变输出电压分量。

3. 发明授权

US06707411B1 Analog-to-digital converter with on-chip memory 有权
标题翻译：具有片上存储器的模数转换器
公开(公告)号：US06707411B1
公开(公告)日：2004-03-16
申请号：US10284890
申请日：2002-10-30
申请人： Kenneth D. Poulton , Thomas E. Kopley , Robert M. R. Neff
发明人： Kenneth D. Poulton , Thomas E. Kopley , Robert M. R. Neff
IPC分类号： H03M300
CPC分类号： G11C7/16 , G06F5/00 , H03M1/1215 , H03M1/127
摘要： The analog-to-digital conversion system comprises an analog-to-digital converter that includes a digital output, memory having a data input and a data output, an output port, an input data bus that extends from the digital output of the analog-to-digital converter to the data input of the memory and an output data bus that extends from the data output of the memory to the output port. The analog-to-digital converter is structured to generate digital samples at a sampling rate. The input data bus is structured to operate at the sampling rate of the ADC. At least one of the data output of the memory, the output data bus and the output port is structured to operate at a maximum rate less than the sampling rate.
摘要翻译：模数转换系统包括模数转换器，其包括数字输出，具有数据输入和数据输出的存储器，输出端口，从模拟 - 数字转换器的数字输出端延伸的输入数据总线，数字转换器到存储器的数据输入以及从存储器的数据输出到输出端口的输出数据总线。模数转换器被构造成以采样率产生数字采样。输入数据总线被构造为以ADC的采样率工作。存储器，输出数据总线和输出端口的数据输出中的至少一个被构造为以低于采样速率的最大速率操作。

4. 发明授权

US06259281B1 Parallel analog sampling circuit and analog-to-digital converter system incorporating clock signal generator generating sub-sampling clock signals with fast and precisely-timed edges 有权
标题翻译：并行模拟采样电路和模数转换器系统，并入时钟信号发生器，产生具有快速精确定时边沿的子采样时钟信号
公开(公告)号：US06259281B1
公开(公告)日：2001-07-10
申请号：US09306339
申请日：1999-05-06
申请人： Robert M. R. Neff
发明人： Robert M. R. Neff
IPC分类号： H03K500
CPC分类号： H03M1/0624 , H03M1/1215
摘要： The analog sampling circuit samples an analog input signal at intervals of time precisely defined by a master clock signal. The analog sampling circuit comprises N track-and-hold circuits and a clock signal generator. Each of the track-and-hold circuits includes a clock signal input. The clock signal generator includes a clock window signal generator and N gate circuits. The clock window signal generator comprises an input connected to receive the master clock signal, and N outputs, derives clock window signals from the master clock signal and feeds one of the clock window signals to each of the outputs. The clock window signals have imprecisely-timed edges. Each of the N gate circuits generates a sub-sampling clock signal with logic states defined by one of the clock window signals and with edge timings defined by the master clock signal independently of the imprecisely-timed edges of the clock window signal, and comprises a first input, a second input and an output. The first input is connected to one of the outputs of the clock window signal generator, the second input is connected to receive the master clock signal and the output is connected to the clock signal input of one of the track-and-hold circuits. The N-channel analog-to-digital conversion system includes the analog sampling circuit just described and an analog-to-digital converter connected to the analog output of the each of the N track-and-hold circuits.
摘要翻译：模拟采样电路以主时钟信号精确定义的时间间隔采样模拟输入信号。模拟采样电路包括N个跟踪保持电路和时钟信号发生器。每个跟踪和保持电路包括时钟信号输入。时钟信号发生器包括时钟窗口信号发生器和N个门电路。时钟窗口信号发生器包括连接以接收主时钟信号的输入端，并且N个输出端从主时钟信号导出时钟窗口信号，并将一个时钟窗口信号馈送到每个输出端。时钟窗口信号具有不精确定时的边沿。 N个门电路中的每一个产生具有由时钟窗信号中的一个定义的逻辑状态的子采样时钟信号，并且与由主时钟信号定义的边缘定时独立于时钟窗信号的不精确定时的边沿，第一输入，第二输入和输出。第一输入连接到时钟窗口信号发生器的一个输出端，第二个输入端连接以接收主时钟信号，输出端连接到其中一个跟踪和保持电路的时钟信号输入端。 N沟道模数转换系统包括刚刚描述的模拟采样电路和连接到N个跟踪和保持电路中的每一个的模拟输出的模数转换器。

5. 发明授权

US06933862B2 Power consumption stabilization system and method 失效
标题翻译：功耗稳定系统及方法
公开(公告)号：US06933862B2
公开(公告)日：2005-08-23
申请号：US10684992
申请日：2003-10-14
申请人： Robert M. R. Neff
发明人： Robert M. R. Neff
IPC分类号： H03K17/16 , H03M7/00 , H04L25/03 , H04L25/49
CPC分类号： H04L25/4906 , H04L25/03866
摘要： A source signal is provided. The source signal is XORed with a scrambling random signal to generate a scrambled signal. The scrambled signal is transmitted through the digital logic circuit. The scrambled signal is XORed with the descrambling random signal logically identical to the scrambling random signal to produce a descrambled signal identical to the source signal. In one embodiment, the scrambling random signal is transmitted through the digital logic circuit and used as the descrambling random signal. In another embodiment, the scrambling random signal and descrambling random signal are generated independently using pseudo-random number generators. In yet another embodiment, the scrambling random signal is self-synchronizing and is contained within the pattern of the scrambled signal.
摘要翻译：提供源信号。源信号与加扰随机信号进行异或以产生加扰信号。加扰信号通过数字逻辑电路传输。加扰信号与解扰乱随机信号进行异或，与扰频随机信号逻辑相同，以产生与源信号相同的解扰信号。在一个实施例中，加扰随机信号通过数字逻辑电路传输并用作解扰随机信号。在另一个实施例中，使用伪随机数发生器独立地生成加扰随机信号和解扰随机信号。在另一个实施例中，加扰随机信号是自同步的并且被包含在加扰信号的模式中。

6. 发明授权

US06720895B2 Method of calibrating an analog-to-digital converter and a circuit implementing the same 有权
标题翻译：校准模数转换器的方法和实现其的电路
公开(公告)号：US06720895B2
公开(公告)日：2004-04-13
申请号：US10061138
申请日：2002-02-01
申请人： Kenneth D. Poulton , Robert M. R. Neff , Matthew S. Holcomb , James Kang
发明人： Kenneth D. Poulton , Robert M. R. Neff , Matthew S. Holcomb , James Kang
IPC分类号： H03M110
CPC分类号： H03M1/1071 , H03M1/0692 , H03M1/1061 , H03M1/447
摘要： A method of calibrating a high-speed analog to digital converter and an ADC that implements the method. Multiple linear regression analysis is used to calibrate the stages of a pipeline ADC to compensate for variations in gain from stage to stage and optionally to compensate for harmonic distortion. Current amplifiers each having gain of about 1.6 are used for low power consumption, minimal surface area requirements, and rapid sampling speed. Weighting factors are stored in lookup tables to minimize the number of adders required to generate the output digital word.
摘要翻译：一种校准高速模数转换器和实现该方法的ADC的方法。多重线性回归分析用于校准流水线ADC的阶段，以补偿从阶段到阶段的增益变化，并可选地补偿谐波失真。每个增益约为1.6的电流放大器用于低功耗，最小表面积要求和快速采样速度。加权因子存储在查找表中以最小化生成输出数字字所需的加法器数量。

7. 发明授权

US06956423B2 Interleaved clock signal generator having serial delay and ring counter architecture 有权
标题翻译：具有串行延迟和环形计数器架构的交错时钟信号发生器
公开(公告)号：US06956423B2
公开(公告)日：2005-10-18
申请号：US10061504
申请日：2002-02-01
申请人： Robert M. R. Neff
发明人： Robert M. R. Neff
IPC分类号： H03K5/15 , H03K5/156 , H03L7/07 , H03L7/081 , G06F1/04
CPC分类号： H03K5/15093 , H03K5/1504 , H03K5/1565 , H03L7/07 , H03L7/0812
摘要： The interleaved clock generator generates N interleaved clock signals in response to an input clock signal. The interleaved clock generator comprises an interleaved clock generator of a first type for receiving the input clock signal and for generating M interleaved intermediate clock signals in response to the input clock signal. The interleaved clock generator of the first type includes either a multi-stage serial-delay circuit or a ring counter circuit. The interleaved clock generator additionally comprises M interleaved clock generators of a second type, each of which is each for receiving a respective one of the intermediate clock signals from the clock generator of the first type and for generating N/M of the N interleaved clock signals in response to the respective one of the intermediate clock signals. Each of the interleaved clock generators of the second type includes either a ring counter circuit or a multi-stage serial-delay circuit: a ring counter when the interleaved clock generator of the first type includes a multi-stage serial-delay circuit; a multi-stage serial-delay circuit when the interleaved clock generator of the first type includes a ring counter circuit.
摘要翻译：交错时钟发生器响应输入时钟信号产生N个交错时钟信号。交错时钟发生器包括第一类型的交错时钟发生器，用于接收输入时钟信号并响应于输入时钟信号产生M个交错的中间时钟信号。第一类型的交错时钟发生器包括多级串行延迟电路或环形计数器电路。交错时钟发生器还包括第二类型的M个交错时钟发生器，每个都是用于从第一类型的时钟发生器接收相应的一个中间时钟信号，并产生N个交错时钟信号的N / M 响应于相应的一个中间时钟信号。第二类型的交错时钟发生器中的每一个包括环形计数器电路或多级串行延迟电路：当第一类型的交错时钟发生器包括多级串行延迟电路时的环形计数器; 当第一类型的交错时钟发生器包括环形计数器电路时的多级串行延迟电路。

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