专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20180191363A1 DIGITAL-TO-ANALOG CONVERSION CIRCUIT 审中-公开
公开(公告)号：US20180191363A1
公开(公告)日：2018-07-05
申请号：US15857651
申请日：2017-12-29
申请人： HUAWEI TECHNOLOGIES CO., LTD.
发明人： Ding LI , Shuai DU , Hongpei WANG
IPC分类号： H03M1/06 , H03M1/40
CPC分类号： H03M1/068 , H03M1/00 , H03M1/1009 , H03M1/406 , H03M1/66 , H03M1/742 , H03M1/745 , H03M1/785
摘要： Embodiments of the present invention provide a digital-to-analog conversion circuit, where the digital-to-analog conversion circuit includes a signal amplitude detector and a digital-to-analog converter. When the signal amplitude detector detects a low signal amplitude, a first current module in the digital-to-analog converter operates normally and a second current module in the digital-to-analog converter stops operating. In addition, when stopping operating, the second current module is in a state of a third bias voltage and a fourth bias voltage that are generated by a second bias circuit. When the amplitude detector detects a high signal amplitude subsequently, the second current module resumes normal operation. After operating normally, the second current module switches back to a first bias voltage and a second bias voltage that are generated by a first bias circuit. This reduces a nonlinearity problem caused before a second current module resumes normal operation.

2. 发明授权

US09998105B2 Programmable switched capacitor block 有权
公开(公告)号：US09998105B2
公开(公告)日：2018-06-12
申请号：US14493635
申请日：2014-09-23
申请人： Cypress Semiconductor Corporation
发明人： Eashwar Thiagarajan , Harold Kutz , Jaskarn Singh Johal , Erhan Hancioglu , Hans Klein , Bruce Byrkett , Mark Hastings , Dennis Seguine , Kendall Castor-Perry , Monte Mar , Gajender Rohilla
IPC分类号： H03M1/12 , H03K17/00 , H03M1/44 , H03M1/46 , H03M1/06
CPC分类号： H03K17/00 , H03H19/00 , H03M1/007 , H03M1/068 , H03M1/18 , H03M1/442 , H03M1/468 , H03M1/70
摘要： A first analog block includes a first plurality of switched capacitors and a second analog block includes a second plurality of switched capacitors. A switch associated with the first plurality of switched capacitors as well as a switch associated with the second plurality of switched capacitors may be configured based on one or more analog functions. The configuring of the first analog and the second analog block may include the configuring of the switch associated with the first plurality of switched capacitors when the analog function is associated with a first single ended signal and the configuring of both the switch associated with the first plurality of switched capacitors and the switch associated with the second plurality of switched capacitors when the analog function is associated with a differential signal.

3. 发明授权

US09209822B2 A/D converter and semiconductor integrated circuit 有权
标题翻译： A / D转换器和半导体集成电路
公开(公告)号：US09209822B2
公开(公告)日：2015-12-08
申请号：US14466399
申请日：2014-08-22
申请人： Kabushiki Kaisha Toshiba
发明人： Chen Kong Teh , Atsushi Suzuki
IPC分类号： H03M1/12 , H03M1/00 , G04F10/00 , H02M3/157
CPC分类号： H03M1/002 , G04F10/005 , H02M3/157 , H03M1/068 , H03M1/12 , H03M1/502
摘要： According to one embodiment, an A/D converter includes a first delay cell column in which a plurality of delay cells, to which a first bias current corresponding to a difference voltage between an input voltage and a reference voltage is supplied, is connected in series. The converter includes a second delay cell column in which a plurality of delay cells, to which a second bias current corresponding to a negative-phase difference voltage of the difference voltage is supplied, is connected in series. The converter includes an encoder unit configured to encode a difference value, in delay time of signal propagation, between the first delay cell column and the second delay cell column.
摘要翻译：根据一个实施例，A / D转换器包括第一延迟单元列，其中提供与输入电压和参考电压之间的差分电压相对应的第一偏置电流的多个延迟单元串联连接。转换器包括第二延迟单元列，其中与供给差分电压的负相位差电压相对应的第二偏置电流的多个延迟单元串联连接。转换器包括：编码器单元，被配置为在第一延迟单元列和第二延迟单元列之间对信号传播的延迟时间中的差值进行编码。

4. 发明授权

US08115663B2 Mismatch-immune digital-to-analog converter 有权
标题翻译：不匹配免疫数模转换器
公开(公告)号：US08115663B2
公开(公告)日：2012-02-14
申请号：US12760187
申请日：2010-04-14
申请人： Joao Pedro Santos Cabrita Marques
发明人： Joao Pedro Santos Cabrita Marques
IPC分类号： H03M1/66
CPC分类号： H03M1/068 , H03M1/827
摘要： In an embodiment, a digital-to-analog converter (DAC) includes inputs for receiving first and second signals encoded as a digital signal pair including overlapping low value portions that are substantially equal in duration to overlapping high value portions, within a frame. The DAC further includes an output terminal for providing an analog signal and includes first and second switches responsive to the first and second signals alter a level of the analog signal based on values of the first and second signals to provide a mismatch-immune DAC functionality. In one instance, the switches couple current sources to a common node. In another instance, the switches configure a resistive network to alter a resistance at an input to an amplifier.
摘要翻译：在一个实施例中，数模转换器（DAC）包括用于接收被编码为数字信号对的第一和第二信号的输入，所述第一和第二信号包括一帧内包括与重叠的高值部分基本相等的重叠低值部分的数字信号对。 DAC还包括用于提供模拟信号的输出端子，并且包括响应于第一和第二信号的第一和第二开关，基于第一和第二信号的值改变模拟信号的电平，以提供失配免疫DAC功能。在一种情况下，交换机将电流源耦合到公共节点。在另一种情况下，开关配置电阻网络以改变放大器输入端的电阻。

5. 发明申请

US20040145506A1 Constant switching for signal processing 有权
标题翻译：信号处理恒定切换
公开(公告)号：US20040145506A1
公开(公告)日：2004-07-29
申请号：US10351470
申请日：2003-01-24
发明人： Bernd Schafferer
IPC分类号： H03M001/66
CPC分类号： H03M1/068 , H03M1/742
摘要： Methods and devices for code independent switching in signal processing circuit such as a digital-to-analog converter (DAC) are described, which provide code independent switching activity. A steering cell receives a digital data input signal that is defined at data intervals, and produces multiple representative analog output signals. For each data interval, each analog output signal depends only on the present state of the digital data input signal, independently of any previous state of the digital data input signal. In addition, the signal processing circuit apart from the analog output signals is substantially free of data dependent disturbances.
摘要翻译：描述了诸如数模转换器（DAC）的信号处理电路中用于代码独立切换的方法和装置，其提供与代码无关的切换活动。转向单元接收以数据间隔定义的数字数据输入信号，并产生多个代表性的模拟输出信号。对于每个数据间隔，每个模拟输出信号仅取决于数字数据输入信号的当前状态，独立于数字数据输入信号的任何先前状态。此外，除了模拟输出信号之外的信号处理电路基本上没有数据相关的干扰。

6. 发明授权

US06198422B1 Low-voltage analog-to-digital converter 有权
标题翻译：低压模数转换器
公开(公告)号：US06198422B1
公开(公告)日：2001-03-06
申请号：US09296493
申请日：1999-04-22
申请人： Dong Won Kim
发明人： Dong Won Kim
IPC分类号： H03M112
CPC分类号： H03M1/068 , H03M1/365
摘要： A low-voltage A/D converter is provided which improves resolution by applying a sampling block at input terminal of a comparator to 0˜Vdd period. The low-voltage A/D converter includes: data input/output terminals consisting of input terminals for respectively inputting a positive reference voltage VREFP, a negative reference voltage VREFN, a positive input value INP and a negative input value INN, and digital data output terminals; resistors connected in series to sequentially level down the positive reference voltage VREFP and the negative reference voltage VREFN input through the data input/output terminals; comparators including a sampling block consisting of NMOS transistors and a sampling block consisting of PMOS transistors, for respectively comparing the positive reference voltage VREFP and the negative reference voltage VREFN leveled down by the resistors with the positive input value INP and the negative input value INN, wherein the sampling block consisting of NMOS transistors outputs the value of low bit comparators and the sampling block consisting of PMOS transistors outputs the value of high bit comparators; and an encoder for encoding the resultant value output from the comparators and outputting the digital converted value.
摘要翻译：提供了一种低电压A / D转换器，通过在比较器的输入端应用0〜Vdd周期来提高分辨率。低电压A / D转换器包括：分别输入正参考电压VREFP，负参考电压VREFN，正输入值INP和负输入值INN的输入端组成的数据输入/输出端子和数字数据输出终端; 电阻串联连接，顺序降低正参考电压VREFP和通过数据输入/输出端输入的负参考电压VREFN; 比较器包括由NMOS晶体管构成的采样块和由PMOS晶体管组成的采样块，用于分别与正输入值INP和负输入值INN分别比较由电阻器下降的正参考电压VREFP和负参考电压VREFN，其中由NMOS晶体管组成的采样块输出低位比较器的值，由PMOS晶体管组成的采样块输出高位比较器的值; 以及编码器，用于对从比较器输出的结果值进行编码并输出数字转换值。

7. 发明授权

US5008675A Digital to analog converter using pulse width modulator for independently setting edge position 失效
标题翻译：使用脉冲宽度调制器的数模转换器可独立设置边沿位置
公开(公告)号：US5008675A
公开(公告)日：1991-04-16
申请号：US414278
申请日：1989-09-29
申请人： Kazuya Toyomaki
发明人： Kazuya Toyomaki
IPC分类号： H03M1/06 , H03M1/82
CPC分类号： H03M1/822 , H03M1/068
摘要： A PWM type D/A converter having a first PWM converter, a second PWM converter and an analog adder. The digital input signals are designated as odd and even numbered input signals and the reference timing points for outputting odd/even numbered input signal are designated as odd/even numbered reference timing points. The first PWM converter receive the digital input signal to output signal whose rising/falling timing point is set at the earlier/later timing, the larger the value of the odd/even numbered input signal relative to the odd/even numbered reference timing point and the pulse width is determined by the values of the odd numbered input signal and the next even numbered input signal. The second PWM converter receives the digital input signal to output signal whose rising/falling timing point is set at the later timing, the larger the value of the even/odd numbered input signal relative to the even/odd numbered reference timing point and the pulse width is determined by the value of the even numbered input signal and the next odd numbered input signal. In another aspect the second PWM converter receives the digital input signal to output signal whose rising/falling timing point is at the later the timing, the larger the value of the odd/even numbered input signal relative to the odd/even numbered reference timing point and the pulse width is determined by complementary values of the odd numbered input signal and the next even numbered input signal.

8. 发明授权

US09806729B1 Current steering cell with code-dependent nonlinearity cancellation and fast settling for low-power low-area high-speed digital-to-analog converters 有权
公开(公告)号：US09806729B1
公开(公告)日：2017-10-31
申请号：US15298141
申请日：2016-10-19
申请人： Marvell International Ltd.
发明人： Alireza Razzaghi , Arvind Anumula Paramanandam , Anuranjan Jha , Weiwei Xu , Xiaoyue Wang
IPC分类号： H03M1/66 , H03M1/06 , H03M1/10 , H03M1/12
CPC分类号： H03M1/0612 , H03M1/068 , H03M1/742
摘要： Systems and techniques relating to a digital-to-analog converter (DAC) are described. A described DAC cell includes a differential switch pair coupled with a cross-coupled switch pair. Gate terminals of the differential switch pair are arranged to respectively receive an input signal to the cell and an inverted version of the input signal to respectively drive the gate terminals of the differential switch pair. Gate terminals of the cross-coupled switch pair are arranged to respectively receive the input signal and the inverted version of the input signal to respectively drive the gate terminals of the cross-coupled switch pair. The cross-coupled switch pair is configured to reduce or eliminate net differential transient current between switch output terminals of the differential switch pair. A current-to-voltage converter coupled with the switch output terminals of the differential switch pair generates a voltage that forms at least a portion of an output of the digital-to-analog converter.

9. 发明授权

US09413381B2 High-speed, low-power reconfigurable voltage-mode DAC-driver 有权
标题翻译：高速，低功耗可重新配置的电压模式DAC驱动器
公开(公告)号：US09413381B2
公开(公告)日：2016-08-09
申请号：US14616566
申请日：2015-02-06
申请人： BROADCOM CORPORATION
发明人： Anand Jitendra Vasani , Ali Nazemi , Jun Cao , Afshin Momtaz
IPC分类号： H03M1/66 , H03M1/68 , H03M1/00 , H03M1/10 , H03M1/74
CPC分类号： H03M1/68 , H03M1/002 , H03M1/068 , H03M1/1028 , H03M1/1047 , H03M1/74 , H03M1/80
摘要： A low-power reconfigurable voltage-mode digital-to-analog converter (DAC) driver circuit includes a first and a second supply voltage and a number of DAC units. Each DAC unit is coupled to a respective bit of a digital input. The DAC units are configured to maintain a constant output impedance. Each DAC unit includes one or more complementary switch pairs that couple first nodes of one or more respective impedances to one of the first or the second supply voltage, based on the respective bit of the digital input. Second nodes of the one or more respective impedances are coupled to an output node.
摘要翻译：低功率可重构电压模式数模转换器（DAC）驱动电路包括第一和第二电源电压以及多个DAC单元。每个DAC单元耦合到数字输入的相应位。 DAC单元配置为保持恒定的输出阻抗。每个DAC单元包括一个或多个互补开关对，其基于数字输入的相应位将一个或多个相应阻抗的第一节点耦合到第一或第二电源电压中的一个。一个或多个相应阻抗的第二节点耦合到输出节点。

10. 发明申请

US20160173269A1 Digital to Analog Converter Cell for Signed Operation 有权
标题翻译：用于签名操作的数模转换器单元
公开(公告)号：US20160173269A1
公开(公告)日：2016-06-16
申请号：US14571531
申请日：2014-12-16
申请人： Intel Corporation
发明人： Franz Kuttner , Michael Fulde
IPC分类号： H04L7/00 , H04L1/22 , H03M1/66
CPC分类号： H04L7/0083 , H03M1/068 , H03M1/0863 , H03M1/66 , H03M1/806 , H04L1/22
摘要： A communication system receives an inputs signal and generates a converted output signal. A control signal selectively activates one or more source cells among an array of cells. The selected source cells generate a first charge package and a second charge package at a cell output terminal for the array of cells to generate the converted output signal. The first charge package and the second charge package are generated during the same clock cycle.
摘要翻译：通信系统接收输入信号并产生转换的输出信号。控制信号选择性地激活单元阵列中的一个或多个源单元。所选择的源单元在单元阵列的单元输出端产生第一充电封装和第二充电封装，以产生转换的输出信号。第一个充电包和第二个充电包在相同的时钟周期内产生。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式