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1. 发明授权

US09306621B2 Transceiver including a high latency communication channel and a low latency communication channel 有权
标题翻译：收发器包括高延迟通信信道和低延迟通信信道
公开(公告)号：US09306621B2
公开(公告)日：2016-04-05
申请号：US14498383
申请日：2014-09-26
申请人： Broadcom Corporation
发明人： Heng Zhang , Mehdi Khanpour , Jun Cao , Chang Liu , Afshin Momtaz
IPC分类号： H04B1/74 , H03D3/02 , H03D3/00 , H04L7/033
CPC分类号： H04B1/745 , H03D3/006 , H03D3/02 , H04L7/033
摘要： Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.
摘要翻译：描述了减少收发器中的延迟的方法，系统和装置。收发器包括高延迟通信信道和被配置为高延迟通信信道的旁路信道的低延迟通信信道。当在低延迟应用中使用收发器时，可以利用低延迟通信信道。通过绕过高延迟通信信道，可以避免其中引入的高等待时间（由于用于减少数字处理的数据速率的许多解除序列化阶段）。当低延迟通信信道用于传递数据时，实现数据速率的增加。可以使用延迟锁定环（DLL）将收发器的发射机时钟与收发器的接收机时钟相位对准，以补偿这些时钟之间的相位偏移的有限公差。

2. 发明授权

US09246670B2 Compact low-power fully digital CMOS clock generation apparatus for high-speed SerDes 有权
标题翻译：紧凑型低功耗全数字CMOS时钟发生装置，用于高速SerDes
公开(公告)号：US09246670B2
公开(公告)日：2016-01-26
申请号：US14637306
申请日：2015-03-03
申请人： BROADCOM CORPORATION
发明人： Mahmoud Reza Ahmadi , Siavash Fallahi , Tamer Ali , Ali Nazemi , Hassan Maarefi , Burak Catli , Afshin Momtaz
IPC分类号： H04L7/033 , H03L7/00 , H03L7/099 , H04L7/00
CPC分类号： H04L7/0331 , H03L7/00 , H03L7/0996 , H04L7/0016
摘要： A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles.
摘要翻译：高速时钟发生器装置包括相位插值器（PI）电路，平滑块和基于反相器的低通滤波器。 PI电路接收具有不同相位角的多个时钟信号，并产生具有正确相位角的输出时钟信号。平滑块平滑具有不同相位角的时钟信号，并产生许多具有改进线性度的平滑时钟信号。基于逆变器的低通滤波器滤波具有不同相位角的时钟信号的谐波。

3. 发明申请

US20150304098A1 MULTILANE SERDES CLOCK AND DATA SKEW ALIGNMENT FOR MULTI-STANDARD SUPPORT 审中-公开
标题翻译： MULTILANE SERDES时钟和数据轴对齐多标准支持
公开(公告)号：US20150304098A1
公开(公告)日：2015-10-22
申请号：US14755127
申请日：2015-06-30
申请人： Broadcom Corporation
发明人： Adesh Garg , Jun Cao , Namik Kocaman , Kuo-J (Nick) Huang , Delong Cui , Afshin Momtaz
IPC分类号： H04L7/00
CPC分类号： H04L7/0025 , G06F1/10 , G06F1/3203 , H04L7/033 , H04L25/14
摘要： A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.
摘要翻译：通信系统可以包括根据一个或多个通信标准操作的多个通信信道。通道可以从一个或多个主时钟信号产生数据时钟。可以使用相位检测器对数据时钟的相位进行校准，以确定各个相位关系，并使用相位内插器来调整各个时钟相位。通信系统可以包括在不同数据时钟频率下操作的通信信道。这些系统可以对它们各自的数据时钟进行分频，以实现用于其相位对准的公共时钟频率。可以禁用相位检测器和相关电路，以在不使用时节省电力。

4. 再颁专利

USRE45557E1 Configurable voltage controlled oscillator system and method including dividing forming a portion of two or more divider paths 有权
标题翻译：可配置的压控振荡器系统和方法，包括形成两个或更多个分频器路径的一部分
公开(公告)号：USRE45557E1
公开(公告)日：2015-06-09
申请号：US13935098
申请日：2013-07-03
申请人： Broadcom Corporation
发明人： Mario Caresosa , Namik Kocaman , Afshin Momtaz
IPC分类号： H03L7/18
CPC分类号： H03L7/18 , H04J3/0685 , H04J2203/0082 , H04J2203/0089 , H04L7/033
摘要： A phase lock loop with multiple divider paths is presented herein. The phase lock loop can be used to provide a wide range of frequencies. The phase lock loop can also be used as a portion of a clock multiplier unit or a clock data and recovery unit.
摘要翻译：本文给出了具有多个分频器路径的锁相环。锁相环可用于提供宽范围的频率。锁相环也可以用作时钟倍增器单元或时钟数据和恢复单元的一部分。

5. 发明授权

US08964907B2 Multi-protocol communications receiver with shared analog front-end 有权
标题翻译：具有共享模拟前端的多协议通信接收器
公开(公告)号：US08964907B2
公开(公告)日：2015-02-24
申请号：US13871831
申请日：2013-04-26
申请人： Broadcom Corporation
发明人： Vivek Pundlik Telang , Hong Chen , Vasudevan Parthasarathy , Jun Cao , Afshin Momtaz , Ali Ghiasi , Chung-Jue Chen
IPC分类号： H03D1/00 , H04L27/06 , H04L27/00 , H04B1/00
CPC分类号： H04L27/0002 , H04B1/0007 , H04B1/406
摘要： According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.
摘要翻译：根据示例性实施例，通信接收机可以包括被配置为放大接收信号的可变增益放大器（VGA），被配置为控制VGA的VGA控制器，耦合到所述接收信号的输出的多个模数转换器 VGA，其中当所述通信接收器被配置为处理第一通信协议的信号时，所述多个ADC电路是可操作的，并且其中当所述通信接收器被配置为处理第二通信协议的信号时，只有所述ADC电路的子集可操作。

6. 发明申请

US20140104086A1 DSP RECEIVER WITH HIGH SPEED LOW BER ADC 有权
标题翻译：具有高速低BER ADC的DSP接收器
公开(公告)号：US20140104086A1
公开(公告)日：2014-04-17
申请号：US13754374
申请日：2013-01-30
申请人： BROADCOM CORPORATION
发明人： Bo Zhang , Ali Nazemi , Mahmoud Reza Ahmadi , Afshin Momtaz , Heng Zhang , Hassan Maarefi
IPC分类号： H03M1/10 , H03M1/36
CPC分类号： H03M1/1009 , H03M1/069 , H03M1/1023 , H03M1/141 , H03M1/188 , H03M1/361
摘要： Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC.
摘要翻译：描述了具有模数转换器（ADC）的DSP接收机的方法和装置，具有高速度，低BER性能，低功率和面积要求。通过解决传统的瓶颈，提高了多路径ADC配置的速度。通过集成校准和错误检测和校正（例如分布式偏移校准和冗余比较器）来提高ADC性能。通过使用低BER整流将传统高速，低BER闪存ADC中的比较器数量减半，功率和面积要求大大降低。

7. 发明申请

US20130121391A1 Adaptive Offset Adjustment Algorithm 有权
标题翻译：自适应偏移调整算法
公开(公告)号：US20130121391A1
公开(公告)日：2013-05-16
申请号：US13734619
申请日：2013-01-04
申请人： Broadcom Corporation
发明人： Namik Kemal Kocaman , Afshin Momtaz , Velu Chellam Pillai , Vivek Telang , Sundararajan Chidambara , Magesh Valliappan
IPC分类号： H04B17/00
CPC分类号： H04B17/21 , H03F3/195 , H03F2200/375 , H03F2200/405 , H04L25/03019 , H04L27/08
摘要： An apparatus and method is disclosed to compensate for one or more offsets in a communications signal. A communications receiver may carry out an offset adjustment algorithm to compensate for the one or more offsets. An initial search procedure determines one or more signal metric maps for one or more selected offset adjustment corrections from the one or more offset adjustment corrections. The offset adjustment algorithm determines one or more optimal points for one or more selected offset adjustment correction based upon the one or more signal maps. The adaptive offset algorithm adjusts each of the one or more selected offset adjustment corrections to their respective optimal points and/or each of one or more non-selected offset adjustment corrections to a corresponding one of a plurality of possible offset corrections to provide one or more adjusted offset adjustment corrections. A tracking mode procedure optimizes the one or more adjusted offset adjustment corrections.
摘要翻译：公开了一种用于补偿通信信号中的一个或多个偏移的装置和方法。通信接收机可以执行偏移调整算法来补偿一个或多个偏移。初始搜索过程从一个或多个偏移调整校正确定一个或多个所选择的偏移调整校正的一个或多个信号度量图。偏移调整算法基于一个或多个信号映射确定一个或多个所选偏移调整校正的一个或多个最优点。自适应偏移算法将一个或多个所选择的偏移调整校正中的每一个调整到其各自的最佳点和/或一个或多个未选择的偏移调整校正中的每一个，以适应多个可能的偏移校正中的对应的一个，以提供一个或多个调整后的偏移调整校正。跟踪模式过程优化一个或多个经调整的偏移调整校正。

8. 发明授权

US09100167B2 Multilane SERDES clock and data skew alignment for multi-standard support 有权
标题翻译：多晶硅SERDES时钟和数据偏移对齐，适用于多标准支持
公开(公告)号：US09100167B2
公开(公告)日：2015-08-04
申请号：US13691482
申请日：2012-11-30
申请人： Broadcom Corporation
发明人： Adesh Garg , Jun Cao , Namik Kocaman , Kuo-J Huang , Delong Cui , Afshin Momtaz
IPC分类号： G06F1/04 , H04L7/033 , G06F1/10 , H04L25/14 , H04L7/00
CPC分类号： H04L7/0025 , G06F1/10 , G06F1/3203 , H04L7/033 , H04L25/14
摘要： A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.
摘要翻译：通信系统可以包括根据一个或多个通信标准操作的多个通信信道。通道可以从一个或多个主时钟信号产生数据时钟。可以使用相位检测器对数据时钟的相位进行校准，以确定各个相位关系，并使用相位内插器来调整各个时钟相位。通信系统可以包括在不同数据时钟频率下操作的通信信道。这些系统可以对它们各自的数据时钟进行分频，以实现用于其相位对准的公共时钟频率。可以禁用相位检测器和相关电路，以在不使用时节省电力。

9. 发明授权

US09077328B1 Method and apparatus for reference-less repeater with digital control 有权
标题翻译：具有数字控制功能的无参考中继器的方法和装置
公开(公告)号：US09077328B1
公开(公告)日：2015-07-07
申请号：US14246836
申请日：2014-04-07
申请人： Broadcom Corporation
发明人： Magesh Valliappan , Afshin Momtaz , Namik Kocaman , Vasudevan Parthasarathy
IPC分类号： H04L27/06 , H03K5/26 , H04L7/033 , H04B7/155
CPC分类号： H03K5/26 , H04B7/155 , H04L7/033
摘要： Reference-less repeating circuits provide significant advantages over repeating circuits requiring external frequency references. These repeating circuits eliminate the need for external frequency references provide significant power, layout, and physical isolation advantages. Digitally controlled reference-less repeating circuits have a relatively narrow frequency detection range, but typically consume significantly less power than analog repeating circuits while providing data rate flexibility, particularly at lower data rates. Due to the narrow frequency detection range of digitally controlled reference-less repeating circuits, efficient frequency estimation techniques allow these circuits to quickly lock to an input signal, and provide an accurate repeated output signal.
摘要翻译：无需外部频率参考的无需重复电路可提供超过重复电路的显着优点。这些重复电路消除了对外部频率参考的需求，提供了显着的功率，布局和物理隔离优势。数字控制的无参考中继电路具有相对较窄的频率检测范围，但是通常比模拟重复电路消耗明显更少的功率，同时提供数据速率灵活性，特别是在较低的数据速率下。由于数字控制的无参考中继电路的窄频率检测范围，有效的频率估计技术允许这些电路快速锁定到输入信号，并提供准确的重复输出信号。

10. 发明授权

US09024659B2 Method and apparatus for passive equalization and slew-rate control 有权
标题翻译：无源均衡和转换速率控制的方法和装置
公开(公告)号：US09024659B2
公开(公告)日：2015-05-05
申请号：US14072641
申请日：2013-11-05
申请人： Broadcom Corporation
发明人： Tamer Ali , Hassan Maarefi , Mahmoud Reza Ahmadi , Afshin Momtaz
IPC分类号： H03K19/094 , H03K17/16 , H04L25/03
CPC分类号： H04L25/03019 , H04L25/0288 , H04L25/03885 , H04L2025/03471 , H04L2025/03681
摘要： A device for passive equalization and slew-rate control of a signal includes a first branch and a second branch. The first branch includes a first driver coupled in series with an equalization capacitor. The second branch includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch. The first branch may be configurable to enable either passive equalization or slew-rate control of the signal based on a mode control signal.
摘要翻译：用于信号的无源均衡和转换速率控制的装置包括第一分支和第二分支。第一分支包括与均衡电容器串联耦合的第一驱动器。第二分支包括与电阻器串联耦合的第二驱动器。第二分支可以与第一分支并联耦合。第一分支可以被配置为基于模式控制信号实现对信号的无源均衡或转换速率控制。

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