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1. 发明授权

US07499372B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07499372B2
公开(公告)日：2009-03-03
申请号：US11420603
申请日：2006-05-26
申请人： Noboru Asauchi , Eitaro Otsuka
发明人： Noboru Asauchi , Eitaro Otsuka
IPC分类号： G11C8/00
CPC分类号： G11C16/10 , G11C16/3454 , G11C2216/14
摘要： When writing 16-bit write data to the memory array 100 which can store data of 8 bits per 1 row, the semiconductor memory device 10 first writes the upper 8 bits to the 1st write restricted row of the memory array 100. The increment controller 150 determines whether or not the value of the existing data written to the memory array 100 and the write data used for writing latched to the 8-bit latch register 170 match. When the existing data and the write data match, the increment controller 150 outputs the write enable signal WEN1 to the write/read controller 140 and executes the writing of the lower 8 bits of write data to the memory array 100.
摘要翻译：当向可存储每1行8位数据的存储器阵列100写入16位写入数据时，半导体存储器件10首先将高8位写入存储器阵列100的第1写入限制行。增量控制器150 确定写入存储器阵列100的现有数据的值和用于写入到8位锁存寄存器170的写入数据是否匹配。当现有数据和写入数据匹配时，增量控制器150将写入使能信号WEN1输出到写入/读取控制器140，并将写入数据的低8位写入存储器阵列100。

2. 发明申请

US20080212379A1 Semiconductor Memory Device 失效
标题翻译：半导体存储器件
公开(公告)号：US20080212379A1
公开(公告)日：2008-09-04
申请号：US11420603
申请日：2006-05-26
申请人： Noboru Asauchi , Eitaro Otsuka
发明人： Noboru Asauchi , Eitaro Otsuka
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C16/3454 , G11C2216/14
摘要： When writing 16-bit write data to the memory array 100 which can store data of 8 bits per 1 row, the semiconductor memory device 10 first writes the upper 8 bits to the 1st write restricted row of the memory array 100. The increment controller 150 determines whether or not the value of the existing data written to the memory array 100 and the write data used for writing latched to the 8-bit latch register 170 match. When the existing data and the write data match, the increment controller 150 outputs the write enable signal WEN1 to the write/read controller 140 and executes the writing of the lower 8 bits of write data to the memory array 100.
摘要翻译：当将16位写数据写入可存储每1行8位数据的存储器阵列100时，半导体存储器件10首先将高8位写入存储器阵列100的第一写限制行。增量控制器150确定写入存储器阵列100的现有数据的值和用于写入到8位锁存寄存器170的写入数据是否匹配。当现有数据和写入数据匹配时，增量控制器150将写入使能信号WEN 1输出到写/读控制器140，并且执行写入数据的低8位的写入到存储器阵列100。

3. 发明申请

US20090225609A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090225609A1
公开(公告)日：2009-09-10
申请号：US12402151
申请日：2009-03-11
申请人： Noboru Asauchi , Eitaro Otsuka
发明人： Noboru Asauchi , Eitaro Otsuka
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C16/06 , G06F21/6218 , H03K23/50
摘要： When the input write data is a value of a value greater than the existing data of the memory array 100, the semiconductor memory device enables writing of input write data to the memory array 100. In specific terms, the increment controller 150 reads the existing data from the memory array 100, and compares it with the write data latched to the 8-bit latch register 170. When the value of the write data is a value greater than the existing data, the increment controller 150 outputs the write enable signal WEN1 to the write/read controller 140, and executes writing of the write data latched to the 8-bit latch register 170 to the memory array 100.
摘要翻译：当输入写入数据是大于存储器阵列100的现有数据的值的值时，半导体存储器件能够将输入写入数据写入存储器阵列100.具体而言，增量控制器150读取现有数据并将其与锁存到8位锁存寄存器170的写入数据进行比较。当写入数据的值大于现有数据时，增量控制器150将写使能信号WEN1输出到写/读控制器140，并且将锁存到8位锁存寄存器170的写数据写入存储器阵列100。

4. 发明申请

US20080144382A1 Semiconductor Memory Device 有权
标题翻译：半导体存储器件
公开(公告)号：US20080144382A1
公开(公告)日：2008-06-19
申请号：US11420535
申请日：2006-05-26
申请人： Noboru Asauchi , Eitaro Otsuka
发明人： Noboru Asauchi , Eitaro Otsuka
IPC分类号： G11C16/06
CPC分类号： G11C16/06 , G06F21/6218 , H03K23/50
摘要： When the input write data is a value of a value greater than the existing data of the memory array 100, the semiconductor memory device enables writing of input write data to the memory array 100. In specific terms, the increment controller 150 reads the existing data from the memory array 100, and compares it with the write data latched to the 8-bit latch register 170. When the value of the write data is a value greater than the existing data, the increment controller 150 outputs the write enable signal WEN1 to the write/read controller 140, and executes writing of the write data latched to the 8-bit latch register 170 to the memory array 100.
摘要翻译：当输入写入数据是大于存储器阵列100的现有数据的值的值时，半导体存储器件能够将输入写入数据写入存储器阵列100。具体来说，增量控制器150从存储器阵列100读取现有数据，并将其与锁存到8位锁存寄存器170的写入数据进行比较。当写入数据的值大于现有数据时，增量控制器150将写入使能信号WEN 1输出到写入/读取控制器140，并且执行锁存到8位锁存器寄存器的写入数据的写入 170到存储器阵列100。

5. 发明授权

US07791979B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07791979B2
公开(公告)日：2010-09-07
申请号：US12402151
申请日：2009-03-11
申请人： Noboru Asauchi , Eitaro Otsuka
发明人： Noboru Asauchi , Eitaro Otsuka
IPC分类号： G11C8/00
CPC分类号： G11C16/06 , G06F21/6218 , H03K23/50
摘要： When the input write data is a value of a value greater than the existing data of the memory array 100, the semiconductor memory device enables writing of input write data to the memory array 100. In specific terms, the increment controller 150 reads the existing data from the memory array 100, and compares it with the write data latched to the 8-bit latch register 170. When the value of the write data is a value greater than the existing data, the increment controller 150 outputs the write enable signal WEN1 to the write/read controller 140, and executes writing of the write data latched to the 8-bit latch register 170 to the memory array 100.
摘要翻译：当输入写入数据是大于存储器阵列100的现有数据的值的值时，半导体存储器件能够将输入写入数据写入存储器阵列100.具体而言，增量控制器150读取现有数据并将其与锁存到8位锁存寄存器170的写入数据进行比较。当写入数据的值大于现有数据时，增量控制器150将写使能信号WEN1输出到写/读控制器140，并且将锁存到8位锁存寄存器170的写数据写入存储器阵列100。

6. 发明授权

US07522470B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07522470B2
公开(公告)日：2009-04-21
申请号：US11420535
申请日：2006-05-26
申请人： Noboru Asauchi , Eitaro Otsuka
发明人： Noboru Asauchi , Eitaro Otsuka
IPC分类号： G11C8/00
CPC分类号： G11C16/06 , G06F21/6218 , H03K23/50
摘要： When the input write data is a value of a value greater than the existing data of the memory array 100, the semiconductor memory device enables writing of input write data to the memory array 100. In specific terms, the increment controller 150 reads the existing data from the memory array 100, and compares it with the write data latched to the 8-bit latch register 170. When the value of the write data is a value greater than the existing data, the increment controller 150 outputs the write enable signal WEN1 to the write/read controller 140, and executes writing of the write data latched to the 8-bit latch register 170 to the memory array 100.
摘要翻译：当输入写入数据是大于存储器阵列100的现有数据的值的值时，半导体存储器件能够将输入写入数据写入存储器阵列100.具体而言，增量控制器150读取现有数据并将其与锁存到8位锁存寄存器170的写入数据进行比较。当写入数据的值大于现有数据时，增量控制器150将写使能信号WEN1输出到写/读控制器140，并且将锁存到8位锁存寄存器170的写数据写入存储器阵列100。

7. 发明授权

US07068566B2 Semiconductor memory device capable of outputting data when a read request not accompanied with an address change being issued 失效
标题翻译：当发出不伴随地址改变的读取请求时能够输出数据的半导体存储器件
公开(公告)号：US07068566B2
公开(公告)日：2006-06-27
申请号：US10834173
申请日：2004-04-29
申请人： Eitaro Otsuka , Koichi Mizugaki
发明人： Eitaro Otsuka , Koichi Mizugaki
IPC分类号： G11C8/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/4076 , G11C2207/2218 , G11C2207/2281 , G11C2207/229 , G11C2211/4061
摘要： The present invention provides a technique of causing a semiconductor device to output data if a read request not accompanied with an address change is issued. In a first situation in which a write request regarding a first data group is issued, a write operation of the first data group for a first group of memory cells among a set of memory cells selected by the current address is executed. When this occurs, a read operation of a second data group for a second group of memory cells among the set of memory cells is executed on a preliminary basis. The second group of memory cells is different from the first group of memory cells. In a second situation in which a read request for the second data group is issued while the current address is being maintained, the second data group that has been read preliminarily and held is externally output without executing a read operation for the second group of memory cells.
摘要翻译：本发明提供了如果发出不伴随地址改变的读取请求，则使半导体器件输出数据的技术。在发出关于第一数据组的写请求的第一种情况下，执行由当前地址选择的一组存储单元中的第一组存储单元的第一数据组的写操作。当发生这种情况时，初步地执行存储器单元组中的第二组存储器单元的第二数据组的读取操作。第二组存储器单元与第一组存储器单元不同。在维持当前地址时发出对第二数据组的读取请求的第二种情况下，已经预先和保持读取的第二数据组被外部输出，而不执行第二组存储器单元的读取操作。

8. 发明申请

US20060062071A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20060062071A1
公开(公告)日：2006-03-23
申请号：US11198334
申请日：2005-08-08
申请人： Masaya Uehara , Eitaro Otsuka
发明人： Masaya Uehara , Eitaro Otsuka
IPC分类号： G11C8/00
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C8/12 , G11C2207/107
摘要： A semiconductor memory device includes: a plurality of memory cells arranged in a matrix; a memory cell array divided into a plurality of blocks; a plurality of read amplifiers, each of which is coupled correspondingly to each of the blocks; and a plurality of latch circuits, each group of which is coupled correspondingly to each of the read amplifiers and includes two or more latch circuits coupled to one another in parallel, wherein, in order to read a plurality of data consecutively from the memory cell array, the data are firstly read from one desired memory cell for each block; the read data are secondly inputted and latched, via the read amplifier corresponding to the same block, to one of the latch circuits included in a group of latch circuits corresponding to the same read amplifier; the data are thirdly read from another desired memory cell, which is different from the memory cell from which the data are formerly read, for each block; the read data are fourthly inputted and latched, via the read amplifier corresponding to the same block, to one of the latch circuits, which is different from the latch circuit to which the data are formerly latched, included in the group of latch circuits corresponding to the same read amplifier; and the latched data are lastly outputted in a desired order from each of the latch circuits having the latched data.
摘要翻译：半导体存储器件包括：以矩阵排列的多个存储单元; 被分成多个块的存储单元阵列; 多个读取放大器，每个读取放大器相应地耦合到每个块; 以及多个锁存电路，每组锁存电路相应地耦合到每个读取放大器并且包括并联耦合到彼此的两个或更多个锁存电路，其中为了从存储器单元阵列连续地读取多个数据首先从每个块的一个期望的存储单元读取数据; 将读取数据通过对应于同一块的读取放大器第二次输入和锁存到与同一读取放大器对应的一组锁存电路中的锁存电路之一; 对于每个块，数据从与之前读取的数据的存储器单元不同的另一所需存储单元第三次读取; 读取数据经由对应于同一块的读取放大器被输入并锁存到与数据先前锁存的锁存电路不同的锁存电路之一中，锁存电路包括在对应于相同的读取放大器; 并且锁存的数据最后以具有锁存数据的每个锁存电路的期望顺序输出。

9. 发明申请

US20060044898A1 Semiconductor memory device and electronic equipment 失效
标题翻译：半导体存储器件和电子设备
公开(公告)号：US20060044898A1
公开(公告)日：2006-03-02
申请号：US11178336
申请日：2005-07-12
申请人： Eitaro Otsuka
发明人： Eitaro Otsuka
IPC分类号： G11C29/00
CPC分类号： G11C29/783
摘要： A semiconductor memory device comprises: a memory cell array having a standard memory cell array part in which dynamic memory cells are arranged in a matrix pattern, and a redundant memory cell array having a redundant memory cell set up to replace a defective memory cell in the standard memory cell array part; an access control part controlling external access operation and refresh access operation regarding the memory cell array; and a redundancy judgment circuit executing redundancy judgment to determine whether the memory cell which is a subject to the external access operation or the refresh access operation is the redundant memory cell or not, controlling so as to access the redundant memory cell, if the subjected memory cell is the redundant memory cell, and controlling so as to access the memory cell in the standard memory cell array, if the subjected memory cell is not the redundant memory cell. In case of executing the redundancy judgment for the refresh access operation by the redundancy judgment circuit and the refresh access operation according to generation of a refresh access request indicating the start of the refresh access operation, if the external access request indicating the start of the external access operation generates during the time from start of redundancy judgment for the refresh access operation until completion of the refresh access operation, the access control part makes the redundancy judgment circuit execute the redundancy judgment for the external access operation in parallel to the refresh access operation, and execute the external access operation after completion of the refresh access operation.
摘要翻译：半导体存储器件包括：具有标准存储单元阵列部分的存储单元阵列，其中动态存储器单元以矩阵模式布置;以及冗余存储单元阵列，其具有冗余存储单元阵列，用于替换所述存储单元阵列中的有缺陷的存储器单元标准存储单元阵列部分; 控制外部访问操作的访问控制部分和关于存储单元阵列的刷新访问操作; 以及冗余判断电路，执行冗余判断，以确定作为外部访问操作或刷新访问操作的对象的存储单元是否是冗余存储单元，如果所访问的存储器被控制，则进行冗余存储单元单元是冗余存储单元，并且如果受保护的存储器单元不是冗余存储单元，则进行控制以访问标准存储单元阵列中的存储单元。在通过冗余判断电路进行刷新访问操作的冗余判断和根据生成表示刷新访问操作开始的刷新访问请求的刷新访问操作的情况下，如果指示外部的开始的外部访问请求访问操作在从刷新访问操作的冗余判断开始到完成刷新访问操作之间的时间期间生成，访问控制部分使冗余判断电路与刷新访问操作并行执行用于外部访问操作的冗余判断，并且在完成刷新访问操作之后执行外部访问操作。

10. 发明申请

US20050002257A1 Semiconductor memory device and electronic device 审中-公开
标题翻译：半导体存储器件和电子器件
公开(公告)号：US20050002257A1
公开(公告)日：2005-01-06
申请号：US10837673
申请日：2004-05-04
申请人： Koichi Mizugaki , Eitaro Otsuka
发明人： Koichi Mizugaki , Eitaro Otsuka
IPC分类号： G11C11/403 , G11C11/406 , G11C7/00
CPC分类号： G11C11/40603 , G11C11/406 , G11C11/40615
摘要： In the semiconductor memory device of the invention, when a write enable signal supplied from an external device changes to an active level representing a data writing request, an access controller triggers execution of a write access operation for a preset time period at a return timing of the write enable signal to an inactive level. This arrangement desirably eliminates the long rate restriction of the semiconductor memory device.
摘要翻译：在本发明的半导体存储器件中，当从外部设备提供的写入使能信号变为表示数据写入请求的有效电平时，访问控制器在返回定时的触发时刻触发执行写入存取操作预设时间段写使能信号为非激活电平。这种布置理想地消除了半导体存储器件的长速率限制。

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