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1. 发明授权

US4748347A Logic coincidence gate, triplet of logic gates and sequential logic circuit using this logic gate 失效
标题翻译：逻辑门，逻辑门的三元组和使用该逻辑门的顺序逻辑电路
公开(公告)号：US4748347A
公开(公告)日：1988-05-31
申请号：US918877
申请日：1986-10-15
申请人： Pham N. Tung
发明人： Pham N. Tung
IPC分类号： H03K19/0952 , H03K19/21 , H03K23/40 , H03K23/66 , H03K19/094 , H03K19/096 , H03K21/17 , H03K27/00
CPC分类号： H03K19/0952 , H03K19/217 , H03K23/40 , H03K23/667
摘要： The invention pertains to programmable fast logic.The logic gate of the invention comprises two parallel-mounted inverters comprising one transistor and one saturable load. The second inverter is powered through a transistor, the electrode gate of which, linked to the drain, is joined to the drain of the first inverter which may have additional inputs (OR function). A triplet of three series-mounted logic gates comprises a programming input at the third gate, a re-looping output and, in the case of a sequence of triplets, re-looping inputs at the first gate of the first triplet. A programmable logic circuit is obtained by a sequence of series-mounted triplets which are all looped back to the first gate of the sequence. The programming is obtained by placing one or two programming inputs at the logic 0 level.Application: Programmable frequency divider circuits in which the ratios follow one another, one by one.
摘要翻译：本发明涉及可编程快速逻辑。本发明的逻辑门包括两个并联安装的反相器，包括一个晶体管和一个饱和负载。第二反相器通过晶体管供电，晶体管的电极栅极连接到漏极，其连接到第一反相器的漏极，第一反相器的漏极可以具有额外的输入（OR功能）。三个串联安装的逻辑门的三元组包括在第三个门处的编程输入，重新循环输出，在三阶组序列的情况下，在第一个三元组的第一个门处重新输入。可编程逻辑电路通过一系列串联安装的三元组获得，它们全部环回到序列的第一个栅极。通过将一个或两个编程输入置于逻辑0电平获得编程。应用：可编程分频器电路，其中比率彼此依次相继。

2. 发明授权

US5027007A FFL/QFL FET logic circuits 失效
标题翻译： FFL / QFL FET逻辑电路
公开(公告)号：US5027007A
公开(公告)日：1991-06-25
申请号：US336709
申请日：1989-04-12
申请人： George S. LaRue , Timothy J. Williams
发明人： George S. LaRue , Timothy J. Williams
IPC分类号： H03K19/0952 , H03K19/21
CPC分类号： H03K19/0952 , H03K19/217
摘要： An FFL/QFL family of logic gates is disclosed, preferably implemented with GaAs MESFET devices and providing enhanced speed-power characteristics. Although a number of gate configurations are disclosed, a NOR gate 26 constructed in accordance with this invention includes a pair of normally OFF input transistors Q1 and Q7, which receive inputs A and B. Current sources Q2 and Q3 couple the transistors to the supply voltage V.sub.DD and ground, respectively. A control transistor Q6 is also coupled to the input and source transistors. An output section 30 responds to the combined operation of transistors Q1, Q2, Q3, Q6, and Q7 to produce an output C in accordance with conventional NOR logic. More particularly, upon application of a high logic input A or B to transistors Q1 and/or Q7, transistors Q1 and/or Q7 and Q6 turn ON and the output C is at a logic low level. If both inputs A and B are low, however, transistors Q1, Q6, and Q7 remain OFF, and the output C is at a high logic level. Use of the control transistor Q6 allows smaller input transistors Q1 and Q7 and current source Q3 to be used, increasing the integration level and gate speed via decreased capacitance.
摘要翻译：公开了一种FFL / QFL逻辑门系列，优选地利用GaAs MESFET器件实现并提供增强的速度功率特性。尽管公开了多个栅极配置，但是根据本发明构造的或非门26包括一对正常关闭的输入晶体管Q1和Q7，其接收输入A和B.电流源Q2和Q3将晶体管耦合到电源电压 VDD和接地。控制晶体管Q6还耦合到输入和晶体管。输出部分30响应于晶体管Q1，Q2，Q3，Q6和Q7的组合操作，以产生根据常规NOR逻辑的输出C. 更具体地，当将高逻辑输入A或B施加到晶体管Q1和/或Q7时，晶体管Q1和/或Q7和Q6导通，输出C处于逻辑低电平。然而，如果两个输入A和B都为低电平，则晶体管Q1，Q6和Q7保持OFF，输出C处于高逻辑电平。使用控制晶体管Q6可以使用更小的输入晶体管Q1和Q7以及电流源Q3，通过降低电容来增加积分电平和栅极速度。

3. 发明授权

US4870305A Circuit for performing the EXCLUSIVE-OR function 失效
标题翻译：执行EXCLUSIVE-OR功能的电路
公开(公告)号：US4870305A
公开(公告)日：1989-09-26
申请号：US141354
申请日：1988-01-06
申请人： Marc Rocchi
发明人： Marc Rocchi
IPC分类号： H03K19/0944 , H03K19/21
CPC分类号： H03K19/217
摘要： A circuit for performing the EXCLUSIVE-OR function of a signal A and a signal B comprises field effect transistors of the MESFET type normally cut off in the absence of a gate-source signal. The circuit also comprises loads and is integrated on a semiconductor substrate of the group III-V. A signal A which is complementary to the signal A is also applied to this circuit. The circuit is formed by a field effect transistor T'.sub.1 whose gate is controlled by the signal B, whose drain receives the signal A via a load R'.sub.1, and whose source receives the signal A which is complementary to the signal A. The signal representing the EXCLUSIVE-OR function (A.sym.B) is available at the junction of the drain of the transistor T'.sub.1 and the load R'.sub.1 and constitutes the output S.sub.1 of the gate.
摘要翻译：用于执行信号A和信号B的EXCLUSIVE-OR功能的电路包括在没有栅极 - 源极信号的情况下通常切断的MESFET型场效应晶体管。该电路还包括负载并集成在III-V族的半导体衬底上。与信号A互补的信号和上行和A也适用于该电路。电路由场效应晶体管T'1形成，其栅极由信号B控制，信号B的漏极通过负载R'1接收信号A，其源极接收与信号A互补的信号和上升沿。表示EXCLUSIVE-OR功能（A（+）B）的信号在晶体管T'1的漏极和负载R'1的结点处可用，并构成栅极的输出S1。

4. 发明授权

US5130763A Integrated semiconductor device with an insulated-gate field effect transistor having a negative transconductance zone 失效
标题翻译：具有负极交叉区域的绝缘栅场效应晶体管的集成半导体器件
公开(公告)号：US5130763A
公开(公告)日：1992-07-14
申请号：US467625
申请日：1990-01-19
申请人： Etienne Delhaye , Michel Wolny , Thierry Aguila , Ramesh Pyndiah
发明人： Etienne Delhaye , Michel Wolny , Thierry Aguila , Ramesh Pyndiah
IPC分类号： H01L29/78 , H01L27/095 , H01L29/80 , H03B19/14 , H03K19/21
CPC分类号： H03B19/14 , H03K19/217
摘要： An integrated semiconductor device, including an insulated-gate field effect transistor biased to a constant level, has a drain-source current characteristic as a function of the gate-source voltage which exhibits a negative transconductance zone beyond a maximum, the slopes of the characteristic on both sides thereof being substantially symmetrical so that two values of the gate-source voltage which are symmetrical with respect to said maximum correspond substantially to the same value of the drain source current, and in that the transistor comprises biasing means ensuring that its operating zone is situated in the region of said characteristic around said maximum.
摘要翻译：包括偏置到恒定电平的绝缘栅场效应晶体管的集成半导体器件具有作为栅极 - 源极电压的函数的漏极 - 源极电流特性，其具有超过最大值的负跨导区域，特性的斜率其两侧基本对称，使得相对于所述最大值对称的栅极 - 源极电压的两个值基本上对应于漏极源电流的相同值，并且晶体管包括偏置装置，确保其工作区域位于围绕所述最大值的所述特征的区域中。

5. 发明授权

US4703204A Logic coincidence gate and logic sequential circuits using said coincidence gate 失效
标题翻译：使用所述符合门的逻辑符合门和逻辑顺序电路
公开(公告)号：US4703204A
公开(公告)日：1987-10-27
申请号：US807731
申请日：1985-12-11
申请人： Ngu T. Pham
发明人： Ngu T. Pham
IPC分类号： H03K19/20 , H03K19/21 , H03K19/017 , H03K19/02 , H03K19/092 , H03K19/094
CPC分类号： H03K19/217
摘要： The invention relates to a coincidence gate, whose output only changes state if the inputs are of the same logic level. It has two parallel-connected NOT circuits, each constituted by a transistor, whose source is at earth and the drain supplied by a resistor, the gates constituting the inputs of the gate. The two resistors are identical saturated resistors and the first NOT circuit is supplied from a fixed voltage, whereas the second NOT circuit is supplied across a Schottky diode connected in the forward direction from the point common to the first saturated resistor and to the drain of the first transistor. The point common to the Schottky diode and the second saturated resistor constitutes the output of the coincidence gate. Application to sequential logic circuits.
摘要翻译：本发明涉及符合门，其输出仅在输入具有相同逻辑电平时才改变状态。它具有两个并联的NOT电路，每个都由晶体管构成，晶体管源源于地，漏极由电阻提供，栅极构成栅极的输入。两个电阻是相同的饱和电阻，第一个NOT电路由一个固定的电压提供，而第二个NOT电路是从正向连接的肖特基二极管上提供的，该肖特基二极管与第一个饱和电阻相同的点连接到第一晶体管。肖特基二极管和第二饱和电阻共同点构成了重合门的输出。应用于顺序逻辑电路。

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