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1. 发明授权

US4215415A Recursive digital filter comprising a circuit responsive to first sum and feedback sign bits and second sum sign and integer bits for detecting overflow in the second sum 失效
标题翻译：递归数字滤波器，包括响应于第一和和反馈符号位的电路，以及用于检测第二和中的溢出的第二和符号和整数位
公开(公告)号：US4215415A
公开(公告)日：1980-07-29
申请号：US943836
申请日：1978-09-19
申请人： Akira Kanemasa , Hisashi Sakaguchi
发明人： Akira Kanemasa , Hisashi Sakaguchi
IPC分类号： H03H17/04 , G06F15/34 , G06F7/48
CPC分类号： H03H17/0405 , H03H17/0461
摘要： In a recursive digital filter for dealing with data words given by two's complement representation in a common word format comprising a sign bit, an integer bit, and a predetermined number of fractional bits, an overflow detect and correct circuit is supplied with simultaneously produced sign bits of bit-serial first sum, feedback, and second sum data words and with the integer bit of the second sum data word and detects overflow in the second sum data word to produce, for use in the circuit, an overflow detect pulse indicative of presence or absence of overflow. In either event, the circuit produces an overflow-free data word for use in the filter. When overflow is detected, the circuit produces a polarity decision pulse that decides polarities of the overflow-free bits. Otherwise, the circuit determines the overflow-free bits directly by the corresponding bits of the second sum data word. Use is preferred of a first and a second timing signal which specify time slots for the sign bit and a prescribed bit, respectively, of each serial data words and which are for directly deciding the overflow-free fractional bits by the polarity decision pulse and for producing a second polarity decision pulse for direct decision of polarities of the overflow-free sign and integer bits. A memory having a plurality of memory areas is preferred for production of the overflow detect and the polarity decision pulses and of the overflow-free bits.
摘要翻译：在用于处理包含符号位，整数位和预定数量的分数位的公共字格式的由二进制补码表示给出的数据字的递归数字滤波器中，溢出检测和校正电路被提供同时产生的符号位比特串行第一和，反馈和第二和数据字和第二和数据字的整数位，并且检测第二和数据字中的溢出，以产生用于电路中的指示存在的溢出检测脉冲或不存在溢出。在任一情况下，该电路产生用于滤波器的无溢出数据字。当检测到溢出时，该电路产生极性决定脉冲，其确定无溢出位的极性。否则，电路直接由第二和数据字的相应位确定无溢出位。使用第一和第二定时信号，分别指定每个串行数据字的符号位和规定位的时隙，并且用于通过极性判定脉冲直接确定无溢出分数位，并且对于产生用于直接决定无溢出符号和整数位的极性的第二极性判定脉冲。具有多个存储区域的存储器优选用于产生溢出检测和极性判定脉冲以及无溢出位。

2. 发明授权

US4935921A Cross-connection network using time switch 失效
标题翻译：交叉网络使用时间开关
公开(公告)号：US4935921A
公开(公告)日：1990-06-19
申请号：US99963
申请日：1987-09-23
申请人： Yasutoshi Ishizaki , Rikio Maruta , Yoshinori Rokugo , Hisashi Sakaguchi , Kuniyasu Hayashi
发明人： Yasutoshi Ishizaki , Rikio Maruta , Yoshinori Rokugo , Hisashi Sakaguchi , Kuniyasu Hayashi
IPC分类号： H04J3/07 , H04Q11/04
CPC分类号： H04J3/073 , H04Q11/04
摘要： In a cross-connection network, a plurality of asynchronous input digital signals can be cross-connected to a plurality of output lines by use of time switch. The input digital signals are pulse stuffed at a common higher bit rate and are synchronized to one another by attaching extra bits. The pulse stuffed signals are assigned into serial frames in a predetermined order by the multiplex technique and are interchanged from one to another by the time switch in the time division fashion. The frame-interchanged signal is demultiplexed to reproduce the pulse-stuffed signals which are sent out to the respective output lines assigned to the frames after removing extra bits. When the input digital signals are of higher order group, each of the higher order group digital signals is demultiplexed to lower order group signals which are pulse stuffed to be synchronized to the common higher bit rate. The pulse stuffed lower order signals are rearranged by the multiplex technique to reform each of the high order group signal which is synchronized to one another. The reformed higher order group signals are assigned in serial frames and are processed in the similar manner as described above. The frame-interchanged signals are reversely processed to be separated, demultiplexed, destuffed, and multiplexed to reproduce the input signals as the output signals.
摘要翻译：在交叉连接网络中，多个异步输入数字信号可以通过使用时间切换与多个输出线交叉连接。输入的数字信号以相同的较高比特率脉冲填充，并通过附加额外的比特来彼此同步。脉冲填充信号通过多路复用技术以预定顺序被分配给串行帧，并且通过时分方式以时分交换方式从一个到另一个互换。帧互换信号被解复用以再现脉冲填充信号，该脉冲填充信号在去除额外位之后发送到分配给帧的相应输出线。当输入数字信号为高阶组时，高阶组数字信号中的每一个被解复用为脉冲填充的较低阶组信号以与公共较高比特率同步。脉冲填充的低阶信号通过多路技术重新排列，以重新形成彼此同步的高阶组信号。改进的高阶组信号以串行帧分配，并以与上述相似的方式进行处理。帧互换的信号被反向处理以被分离，解复用，解消融和多路复用以再现作为输出信号的输入信号。

3. 发明授权

US5144620A Cross-connection network using time switch 失效
标题翻译：交叉网络使用时间开关
公开(公告)号：US5144620A
公开(公告)日：1992-09-01
申请号：US478879
申请日：1990-02-08
申请人： Yasutoshi Ishizaki , Rikio Maruta , Yoshinori Rokugo , Hisashi Sakaguchi , Kuniyasu Hayashi
发明人： Yasutoshi Ishizaki , Rikio Maruta , Yoshinori Rokugo , Hisashi Sakaguchi , Kuniyasu Hayashi
IPC分类号： H04J3/07 , H04Q11/04
CPC分类号： H04J3/073 , H04Q11/04
摘要： An internal frame signal producing circuit for use in a cross connection system which cross connects first bit rate signals, each produced by multiplexing m second bit rate signals at first or the second bit rate signal levels, the first bit rate being higher than the second bit rate, an internal frame frequency is predetermined to be equal to a frequency f.sub.h ' higher than a first nominal frequency f.sub.h of the first bit rate digital signals by a predetermined value, the frequency f.sub.h ' being synchronized with a second nominal frequency fl of the second bit rate digital signals. In order to obtain the internal frame signal, from m second bit rate signals, the m second bit rate signals are stuff-synchronized processed to produce m stuff-synchronized signals, each having a stuff bit, a variable bit, and vacant bit at suitable bit intervals in a frame of a frame length. The m stuffed-synchronized signals are serially arranged to make the internal frame signal. In order to compensate a frequency difference between f.sub.h ' and fl, one frame consisting of all vacant bits is assigned at predetermined frame intervals.
摘要翻译：一种在交叉连接系统中使用的内部帧信号产生电路，其交叉连接第一比特率信号，每个第一比特率信号通过首先复用m个第二比特率信号或第二比特率信号电平而产生，第一比特率高于第二比特率将内部帧频预定为等于比第一比特率数字信号的第一标称频率fh高出预定值的频率fh'，频率fh'与第二位速率数字信号的第二标称频率f1同步比特率数字信号。为了获得内部帧信号，从m个第二比特率信号中，m个第二比特率信号被填充同步处理以产生m个同步信号，每个信号具有适当的填充位，可变位和空闲位帧长度的帧中的位间隔。 m个填充同步信号被串行排列以产生内部帧信号。为了补偿fh'和fl之间的频率差异，以预定的帧间隔分配由所有空位组成的一帧。

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