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1. 发明授权

US07994863B2 Electronic system having common mode voltage range enhancement 有权
标题翻译：具有共模电压范围增强的电子系统
公开(公告)号：US07994863B2
公开(公告)日：2011-08-09
申请号：US12347155
申请日：2008-12-31
申请人： Edmund M. Schneider , Murari L. Kejariwal , Stephen T. Hodapp , John L. Melanson
发明人： Edmund M. Schneider , Murari L. Kejariwal , Stephen T. Hodapp , John L. Melanson
IPC分类号： H03F3/04
CPC分类号： H03F3/45955 , H03F3/005
摘要： An electronic system generates at least one floating supply voltage, wherein during operation of the circuit the floating supply voltage tracks a common mode voltage of first and second differential input signals. By tracking the common mode voltage, in at least one embodiment, the floating supply voltage adjusts as the common mode voltage changes. Thus, the floating supply voltages can be based upon the peak-to-peak values of the first and second output signals without factoring in the common mode voltage. In at least one embodiment, the electronic system provides the floating supply voltages to an amplifier. The amplifier amplifies the first and second differential input signals and generates differential output signals. A differential sampling circuit samples the differential output signals to cancel the common mode voltage from the differential output signals. In at least one embodiment, an analog-to-digital converter converts the sampled differential output signals into a digital output signal.
摘要翻译：电子系统产生至少一个浮动电源电压，其中在电路运行期间，浮动电源电压跟踪第一和第二差分输入信号的共模电压。通过跟踪共模电压，在至少一个实施例中，浮动电源电压随着共模电压的变化而调整。因此，浮动电源电压可以基于第一和第二输出信号的峰 - 峰值而不考虑共模电压。在至少一个实施例中，电子系统向放大器提供浮动电源电压。放大器放大第一和第二差分输入信号并产生差分输出信号。差分采样电路对差分输出信号进行采样，以从差分输出信号中消除共模电压。在至少一个实施例中，模数转换器将采样的差分输出信号转换成数字输出信号。

2. 发明授权

US06317068B1 Method and apparatus for matching common mode output voltage at a switched-capacitor to continuous-time interface 失效
标题翻译：将开关电容器上的共模输出电压与连续时间接口相匹配的方法和装置
公开(公告)号：US06317068B1
公开(公告)日：2001-11-13
申请号：US09378993
申请日：1999-08-23
申请人： Amit Gattani , Paul James Hurst , David William Cline
发明人： Amit Gattani , Paul James Hurst , David William Cline
IPC分类号： H03M166
CPC分类号： H03F3/45937 , H03F3/45475 , H03F3/45955 , H03F3/45977 , H03F2200/331 , H03F2203/45402 , H03F2203/45418 , H03F2203/45424 , H03F2203/45441
摘要： A method and apparatus for matching common mode output voltage at a switched-capacitor to continuous-time interface. An active continuous time summation circuit is used at the output of the switched-capacitor stage to derive the common mode level that is at the output of the switched-capacitor stage. This derived signal is filtered to remove any noise component remaining in it, and is then used as the reference common mode signal in the continuous time stage. This forces the output common mode, and hence the input common mode of the unity gain amplifier stage, to track the common mode output of the switched-capacitor stage. This adaptive tracking eliminates the common mode interface error, which could be present and could vary from die to die (due to parasitic variations). This technique ensures proper tracking of the DC levels between the negative and the positive terminals of the unity gain amplifier, which is essential for low distortion operation of the amplifier.
摘要翻译：一种用于将开关电容器处的共模输出电压与连续时间接口相匹配的方法和装置。在开关电容器级的输出端使用有源连续时间求和电路以得出在开关电容器级的输出处的共模电平。对该导出信号进行滤波以去除其中剩余的任何噪声成分，然后在连续时间段中用作参考共模信号。这迫使输出共模，从而强制单位增益放大器级的输入共模以跟踪开关电容级的共模输出。这种自适应跟踪消除了共模接口错误，其可能存在并且可以随着模具（由于寄生变化）而变化。该技术确保对单位增益放大器的负极和正极之间的直流电平进行适当的跟踪，这对放大器的低失真运算至关重要。

3. 发明授权

US09912310B2 Differential signal conditioner with common mode voltage error compensation 有权
公开(公告)号：US09912310B2
公开(公告)日：2018-03-06
申请号：US15212473
申请日：2016-07-18
申请人： Hamilton Sundstrand Corporation
发明人： James Saloio, Jr. , Robert D. Klapatch
IPC分类号： H03F3/45 , H03G3/30
CPC分类号： H03F3/45479 , H03F3/45955 , H03F2200/471 , H03F2203/45068 , H03F2203/45078 , H03F2203/45212 , H03G3/30
摘要： A differential signal conditioner circuit with common mode voltage (CMV) compensation is provided. The circuit includes a signal multiplexer that receives a input signal that includes a high and low signal and a reference CMV signal, a differential amplifier coupled to the signal multiplexer that receives the reference CMV signal and outputs a CMV error value during a first cycle, and receives the input signal and outputs an amplified difference signal during a second cycle. The circuit also includes a CMV measurement circuit that receives the reference CMV signal and outputs a confirmation value during the first cycle, and receives the input signal and outputs a CMV compensation value during the second cycle, and a processing element that receives the CMV error value, the amplified difference signal, the CMV compensation value, and a differential amplifier gain value and generates a CMV compensated output based on the received signals and values.

4. 发明申请

US20020113626A1 Differential line driver having adjustable common mode operation 有权
标题翻译：差分线路驱动器具有可调共模运行
公开(公告)号：US20020113626A1
公开(公告)日：2002-08-22
申请号：US09790780
申请日：2001-02-22
申请人： Sigma Tel, Inc.
发明人： Matthew D. Felder
IPC分类号： H03K005/153
CPC分类号： H03K5/082 , H03F3/45955 , H03K5/007
摘要： A differential line driver that includes a 1st operational amplifier, a 2nd operational amplifier, an adjustable reference module, a 1st feedback impedance, and a 2nd feedback impedance. First inputs (e.g. the inverting input or non-inverting input) of the 1st and 2nd operational amplifiers are coupled to receive an input signal. The 2nd inputs (e.g. the compliment of the 1st input) of the 1st and 2nd operational amplifiers are operably coupled to receive an adjustable reference voltage from the adjustable reference module. The adjustable reference module provides the adjustable reference voltage based on the common mode of the power source for the 1st and 2nd operational amplifiers (e.g. Vdd, Vss,) and/or the common mode of the input signal. The 1st and 2nd feedback impedances, (e.g. resistors) are coupled from the output of the respective operational amplifiers to either the 1st or 2nd input of the respective operational amplifiers.
摘要翻译：差分线路驱动器，包括第一运算放大器，第二运算放大器，可调参考模块，第一反馈阻抗和第二反馈阻抗。第一和第二运算放大器的第一输入（例如，反相输入或非反相输入）被耦合以接收输入信号。第一和第二运算放大器的第二输入（例如，第一输入的补码）可操作地耦合以从可调参考模块接收可调参考电压。可调参考模块基于用于第一和第二运算放大器（例如Vdd，Vss）的电源的共模和/或输入信号的共模提供可调参考电压。第一和第二反馈阻抗（例如电阻器）从相应运算放大器的输出耦合到相应运算放大器的第一或第二输入端。

5. 发明授权

US5859564A Differential amplifier circuit for use in a read channel for a magnetic recording system 失效
标题翻译：用于磁记录系统的读通道的差分放大器电路
公开(公告)号：US5859564A
公开(公告)日：1999-01-12
申请号：US892776
申请日：1997-07-15
申请人： Jeffrey Lee Sonntag , Suharli Tedja
发明人： Jeffrey Lee Sonntag , Suharli Tedja
IPC分类号： G11B5/02 , G11B20/10 , H03F1/32 , H03F3/16 , H03F3/45
CPC分类号： G11B20/10009 , H03F1/3211 , H03F1/3223 , H03F3/45479 , H03F3/4565 , H03F3/45708 , H03F3/45937 , H03F3/45955 , H03F2203/45524
摘要： Briefly, in accordance with one embodiment of the invention, a circuit includes: at least one differential amplifier. The differential amplifier is coupled in a circuit configuration so that the differential output voltage signal of the differential amplifier circuit includes a scalable second-order harmonic component of the differential input voltage signal applied to the differential amplifier circuit. Briefly, in accordance with another embodiment of the invention, a method of applying a differential input voltage signal to a differential amplifier circuit to produce a differential output voltage signal includes the step of: driving the differential amplifier circuit so that the differential output voltage signal of the differential amplifier circuit includes a second-order harmonic component of the differential input voltage signal.
摘要翻译：简而言之，根据本发明的一个实施例，电路包括：至少一个差分放大器。差分放大器以电路配置耦合，使得差分放大器电路的差分输出电压信号包括施加到差分放大器电路的差分输入电压信号的可扩展二阶谐波分量。简而言之，根据本发明的另一实施例，将差分输入电压信号施加到差分放大器电路以产生差分输出电压信号的方法包括以下步骤：驱动差分放大器电路，使得差分输出电压信号差分放大器电路包括差分输入电压信号的二次谐波分量。

6. 发明申请

US20120249243A1 LOW SWITCHING ERROR, SMALL CAPACITORS, AUTO-ZERO OFFSET BUFFER AMPLIFIER 有权
标题翻译：低开关错误，小电容，自动零偏移缓冲放大器
公开(公告)号：US20120249243A1
公开(公告)日：2012-10-04
申请号：US13413599
申请日：2012-03-06
申请人： Gabriel Rosca
发明人： Gabriel Rosca
IPC分类号： H03F3/45
CPC分类号： H03F3/72 , H03F3/45475 , H03F3/45955 , H03F3/45968
摘要： Switching error in an auto-zero offset amplifier is reduced by keeping a clock level to the auto-zero switches at an amplitude just enough to insure complete switching of the switches of the auto-zero offset buffer amplifier. A level shifting circuit provides the clock at the desired level control and a local voltage regulator provides a regulated voltage to the level shifting circuit.
摘要翻译：通过将自动归零开关的时钟电平保持在刚好足以确保自动调零偏移缓冲放大器的开关的完全切换的幅度，从而降低自动归零失调放大器的开关误差。电平移位电路将时钟提供到期望的电平控制，并且本地电压调节器向电平移位电路提供调节电压。

7. 发明申请

US20100164631A1 ELECTRONIC SYSTEM HAVING COMMON MODE VOLTAGE RANGE ENHANCEMENT 有权
标题翻译：具有共模电压范围增强的电子系统
公开(公告)号：US20100164631A1
公开(公告)日：2010-07-01
申请号：US12347155
申请日：2008-12-31
申请人： Edmund M. Schneider , Murari L. Kejariwal , Stephen T. Hodapp , John L. Melanson
发明人： Edmund M. Schneider , Murari L. Kejariwal , Stephen T. Hodapp , John L. Melanson
IPC分类号： H03F3/04
CPC分类号： H03F3/45955 , H03F3/005
摘要： An electronic system generates at least one floating supply voltage, wherein during operation of the circuit the floating supply voltage tracks a common mode voltage of first and second differential input signals. By tracking the common mode voltage, in at least one embodiment, the floating supply voltage adjusts as the common mode voltage changes. Thus, the floating supply voltages can be based upon the peak-to-peak values of the first and second output signals without factoring in the common mode voltage. In at least one embodiment, the electronic system provides the floating supply voltages to an amplifier. The amplifier amplifies the first and second differential input signals and generates differential output signals. A differential sampling circuit samples the differential output signals to cancel the common mode voltage from the differential output signals. In at least one embodiment, an analog-to-digital converter converts the sampled differential output signals into a digital output signal.
摘要翻译：电子系统产生至少一个浮动电源电压，其中在电路运行期间，浮动电源电压跟踪第一和第二差分输入信号的共模电压。通过跟踪共模电压，在至少一个实施例中，浮动电源电压随着共模电压的变化而调整。因此，浮动电源电压可以基于第一和第二输出信号的峰 - 峰值而不考虑共模电压。在至少一个实施例中，电子系统向放大器提供浮动电源电压。放大器放大第一和第二差分输入信号并产生差分输出信号。差分采样电路对差分输出信号进行采样，以从差分输出信号中消除共模电压。在至少一个实施例中，模数转换器将采样的差分输出信号转换成数字输出信号。

8. 发明授权

US3423689A Direct current amplifier 失效
标题翻译：直流电流放大器
公开(公告)号：US3423689A
公开(公告)日：1969-01-21
申请号：US3423689D
申请日：1965-08-19
申请人： HEWLETT PACKARD CO
发明人： MILLER ARTHUR , LEVIN MORTON H
IPC分类号： H03F3/45 , H03F1/00
CPC分类号： H03F3/45955 , H03F3/45475

9. 发明申请

US20180019718A1 DIFFERENTIAL SIGNAL CONDITIONER WITH COMMON MODE VOLTAGE ERROR COMPENSATION 有权
公开(公告)号：US20180019718A1
公开(公告)日：2018-01-18
申请号：US15212473
申请日：2016-07-18
申请人： Hamilton Sundstrand Corporation
发明人： James Saloio, JR. , Robert D. Klapatch
IPC分类号： H03F3/45 , H03G3/30
CPC分类号： H03F3/45479 , H03F3/45955 , H03F2200/471 , H03F2203/45068 , H03F2203/45078 , H03F2203/45212 , H03G3/30
摘要： A differential signal conditioner circuit with common mode voltage (CMV) compensation is provided. The circuit includes a signal multiplexer that receives a input signal that includes a high and low signal and a reference CMV signal, a differential amplifier coupled to the signal multiplexer that receives the reference CMV signal and outputs a CMV error value during a first cycle, and receives the input signal and outputs an amplified difference signal during a second cycle. The circuit also includes a CMV measurement circuit that receives the reference CMV signal and outputs a confirmation value during the first cycle, and receives the input signal and outputs a CMV compensation value during the second cycle, and a processing element that receives the CMV error value, the amplified difference signal, the CMV compensation value, and a differential amplifier gain value and generates a CMV compensated output based on the received signals and values.

10. 发明授权

US08698556B2 Low switching error, small capacitors, auto-zero offset buffer amplifier 有权
标题翻译：低开关误差，小电容，自动补零缓冲放大器
公开(公告)号：US08698556B2
公开(公告)日：2014-04-15
申请号：US13413599
申请日：2012-03-06
申请人： Gabriel Rosca
发明人： Gabriel Rosca
IPC分类号： H03F1/14 , H03F1/02 , H03F3/72
CPC分类号： H03F3/72 , H03F3/45475 , H03F3/45955 , H03F3/45968
摘要： Switching error in an auto-zero offset amplifier is reduced by keeping a clock level to the auto-zero switches at an amplitude just enough to insure complete switching of the switches of the auto-zero offset buffer amplifier. A level shifting circuit provides the clock at the desired level control and a local voltage regulator provides a regulated voltage to the level shifting circuit.
摘要翻译：通过将自动归零开关的时钟电平保持在刚好足以确保自动调零偏移缓冲放大器的开关的完全切换的幅度，从而降低自动归零失调放大器的开关误差。电平移位电路将时钟提供到期望的电平控制，并且本地电压调节器向电平移位电路提供调节电压。

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