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1. 发明授权

US08390366B2 Charge pump stage, method for controlling a charge pump stage and memory having a charge pump stage 有权
标题翻译：电荷泵级，控制电荷泵级的方法和具有电荷泵级的存储器
公开(公告)号：US08390366B2
公开(公告)日：2013-03-05
申请号：US12955809
申请日：2010-11-29
申请人： Santi Nunzio Antonino Pagano , Francesco La Rosa , Alfredo Signorello
发明人： Santi Nunzio Antonino Pagano , Francesco La Rosa , Alfredo Signorello
IPC分类号： G05F1/10
CPC分类号： G11C5/145 , H03K5/1534 , H03K5/2481
摘要： A charge pump having a supply terminal, for receiving a supply voltage, and an output terminal, for supplying an output voltage. The charge pump has a control block including a comparator having a first comparison input, for receiving the supply voltage, a second comparison input, for receiving the output voltage, and a comparison output, for generating a pump-switch-off signal depending upon a comparison between the input voltage and the output voltage; and a switch controlled in switching off by the pump-switch-off signal and configured for switching off the charge pump circuit. The control block has an activation input for receiving an activation signal that has a plurality of pulses and repeatedly activates the comparator-circuit block.
摘要翻译：具有用于接收电源电压的电源端子和用于提供输出电压的输出端子的电荷泵。电荷泵具有控制块，该控制块包括具有用于接收电源电压的第一比较输入的比较器，用于接收输出电压的第二比较输入和用于产生取决于所述输出电压的泵浦关闭信号的比较输出输入电压与输出电压的比较; 以及由泵关断信号切断并被配置为关闭电荷泵电路的开关。控制块具有用于接收具有多个脉冲的激活信号的激活输入并且重复地激活比较器电路块。

2. 发明申请

US20120250417A1 HOT ELECTRON INJECTION NANOCRYSTALS MOS TRANSISTOR 有权
标题翻译：热电子注入纳米晶体MOS晶体管
公开(公告)号：US20120250417A1
公开(公告)日：2012-10-04
申请号：US13439140
申请日：2012-04-04
申请人： Francesco La Rosa
发明人： Francesco La Rosa
IPC分类号： H01L29/775 , H01L27/088 , G11C16/04
CPC分类号： G11C16/10 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/7885
摘要： The disclosure relates to a hot electron injection MOS transistor, comprising source and drain regions formed in a semiconductor substrate, a control gate, and a floating gate comprising electrically conductive nanoparticles. The control gate comprises a first portion arranged at a first distance from the substrate, a second portion arranged at a second distance less than the first distance from the substrate, and an intermediary portion linking the first and the second portions.
摘要翻译：本发明涉及一种热电子注入MOS晶体管，其包括形成在半导体衬底中的源极和漏极区域，控制栅极和包括导电纳米颗粒的浮动栅极。所述控制栅极包括布置在距离所述衬底第一距离的第一部分，第二部分以比所述衬底的第一距离小的第二距离布置，以及连接所述第一部分和所述第二部分的中间部分。

3. 发明授权

US08036020B2 Circuit for reading a charge retention element for a time measurement 有权
标题翻译：读取电荷保留元件进行时间测量的电路
公开(公告)号：US08036020B2
公开(公告)日：2011-10-11
申请号：US12374794
申请日：2007-07-20
申请人： Francesco La Rosa
发明人： Francesco La Rosa
IPC分类号： G11C11/24
CPC分类号： G11C7/06 , G04F10/10 , G11C7/062
摘要： A method and a circuit for reading an electronic charge retention element for a temporal measurement, of the type including at least one capacitive element whose dielectric exhibits a leakage and a transistor with insulated control terminal for reading the residual charges, the reading circuit including; two parallel branches between two supply terminals, each branch including at least one transistor of a first type and one transistor of a second type, the transistor of the second type of one of the branches consisting of that of the element to be read and the transistor of the second type of the other branch receiving, on its control terminal, a staircase signal, the respective drains of the transistors of the first type being connected to the respective inputs of a comparator whose output provides an indication of the residual voltage in the charge retention element.
摘要翻译：一种用于读取用于时间测量的电子电荷保持元件的方法和电路，包括其电介质具有泄漏的至少一个电容元件和具有用于读取剩余电荷的绝缘控制端的晶体管，所述读取电路包括：两个电源端子之间的两个并联支路，每个支路包括至少一个第一类型晶体管和一个第二类晶体管，第二类型的晶体管中的一个分支由待读取元件和晶体管组成第二类型的第二类型的另一个分支在其控制终端处接收一个阶梯信号，第一类晶体管的各个漏极连接到比较器的各个输入，比较器的输出提供充电中的残余电压的指示保留元件。

4. 发明申请

US20110026346A1 SELF-TIMED LOW POWER SENSE AMPLIFIER 有权
标题翻译：自定时低功率检测放大器
公开(公告)号：US20110026346A1
公开(公告)日：2011-02-03
申请号：US12844472
申请日：2010-07-27
申请人： Francesco La Rosa
发明人： Francesco La Rosa
IPC分类号： G11C7/06 , H03F3/45
CPC分类号： G11C16/28 , G11C7/065 , G11C7/08
摘要： A sense amplifier is disclosed comprising a first sense input, a second sense input, a latch, a first p-channel control transistor arranged to electrically power a first section of the latch and having a gate terminal linked to the first sense input, and a second p-channel control transistor arranged to electrically power a second section of the latch and having a gate terminal linked to the second sense input. Application may be in particular to low power embedded memories.
摘要翻译：公开了一种读出放大器，包括第一感测输入，第二感测输入，锁存器，第一p沟道控制晶体管，被配置为对锁存器的第一部分供电并且具有链接到第一感测输入端的栅极端子，以及第二p沟道控制晶体管，其布置成对所述锁存器的第二部分供电并且具有链接到所述第二检测输入的栅极端子。应用可能特别是低功率嵌入式存储器。

5. 发明申请

US20100054038A1 PROGRAMMING OF A CHARGE RETENTION CIRCUIT FOR A TIME MEASUREMENT 有权
标题翻译：用于时间测量的充电保持电路的编程
公开(公告)号：US20100054038A1
公开(公告)日：2010-03-04
申请号：US12374793
申请日：2007-07-20
申请人： Francesco La Rosa
发明人： Francesco La Rosa
IPC分类号： G11C14/00 , G11C11/24
CPC分类号： G11C27/024 , G04F10/10 , G11C27/005
摘要： A method of controlling an electronic charge retention circuit for time measurement, including at least a first capacitive element, the dielectric of which has a leakage, and at least a second capacitive element, the dielectric of which has a higher capacitance than the first, the two elements having a common electrode defining a floating node that can be connected to an element for measuring its residual charge, in which a charge retention period is programmed or initialized by injecting or extracting charges via the first element.
摘要翻译：一种控制用于时间测量的电子电荷保持电路的方法，包括其电介质具有泄漏的至少第一电容元件和至少第二电容元件，其电介质具有比第一电容元件高的电容两个元件具有限定浮动节点的公共电极，其可以连接到用于测量其剩余电荷的元件，其中通过经由第一元件注入或提取电荷对电荷保留期进行编程或初始化。

6. 发明申请

US20100027334A1 EEPROM CHARGE RETENTION CIRCUIT FOR TIME MEASUREMENT 有权
标题翻译： EEPROM充电保持电路，用于时间测量
公开(公告)号：US20100027334A1
公开(公告)日：2010-02-04
申请号：US12374795
申请日：2007-07-20
申请人： Francesco La Rosa
发明人： Francesco La Rosa
IPC分类号： G11C16/04
CPC分类号： G11C16/22 , G04F10/10 , G11C16/0441 , G11C16/26
摘要： An electronic charge retention circuit for time measurement, implanted in an array of EEPROM memory cells, each including a selection transistor in series with a floating-gate transistor, the circuit including, on any one row of memory cells: a first subassembly of at least a first cell, the thickness of the dielectric of the tunnel window of the floating-gate transistor of which is less than that of the other cells; a second subassembly of at least a second cell, the drain and source of the floating-gate transistor of which are interconnected; a third subassembly of at least a third cell; and a fourth subassembly of at least a fourth cell, the tunnel window of which is omitted, the respective floating gates of the transistors of the cells of the four subassemblies being interconnected.
摘要翻译：一种用于时间测量的电子电荷保持电路，其被注入到EEPROM存储单元的阵列中，每个EEPROM阵列包括与浮栅晶体管串联的选择晶体管，所述电路包括在任何一行存储器单元上：至少第一子组件第一单元，其浮栅晶体管的隧道窗的电介质的厚度小于其它单元的电介质的厚度; 至少第二单元的第二子组件，其浮置晶体管的漏极和源极相互连接; 至少第三单元的第三子组件; 以及至少第四单元的第四子组件，其通道窗口被省略，四个子组件的单元的晶体管的相应浮动栅互连。

7. 发明申请

US20080273400A1 FAST ERASABLE NON-VOLATILE MEMORY 有权
标题翻译：快速易损的非易失性存储器
公开(公告)号：US20080273400A1
公开(公告)日：2008-11-06
申请号：US12113692
申请日：2008-05-01
申请人： Francesco La Rosa , Antonino Conte
发明人： Francesco La Rosa , Antonino Conte
IPC分类号： G11C16/06
CPC分类号： G11C16/225 , G11C16/102
摘要： A method writes data in a non-volatile memory comprising a main memory area comprising target locations, and an auxiliary memory area comprising auxiliary locations. The method comprises a write-erase cycle comprising: reading an initial set of data in a source location located in the main or auxiliary memory area; inserting the piece of data to be written into the initial set of data, to obtain an updated set of data, partially erasing a first group of auxiliary locations and a group of target locations designated by locations of a second group of auxiliary locations, and writing, in an erased auxiliary location of a third group of auxiliary locations, the updated set of data and the address of the target location. The method is particularly applicable to FLASH memories.
摘要翻译：一种方法将数据写入非易失性存储器，包括包括目标位置的主存储区域和包括辅助位置的辅助存储区域。该方法包括写擦除周期，包括：在位于主或辅助存储器区域的源位置读取初始数据集; 将待写入的数据片段插入到初始数据集中，以获得更新的数据集，部分地擦除辅助位置的第一组和由第二组辅助位置的位置指定的一组目标位置，以及写入在第三组辅助位置的擦除辅助位置中，更新的数据集和目标位置的地址。该方法特别适用于闪速存储器。

8. 发明申请

US20080002474A1 EEPROM MEMORY HAVING AN IMPROVED RESISTANCE TO THE BREAKDOWN OF TRANSISTORS 有权
标题翻译：具有对断路器的改进电阻的EEPROM存储器
公开(公告)号：US20080002474A1
公开(公告)日：2008-01-03
申请号：US11754707
申请日：2007-05-29
申请人： Francesco La Rosa
发明人： Francesco La Rosa
IPC分类号： G11C11/34
CPC分类号： G11C16/0433 , H01L27/115
摘要： The present invention relates to a method for programming or erasing memory cells that include a selection transistor connected to a floating-gate transistor. According to the method, a non-zero compensation voltage is applied to the gate of a transistor not involved in the programming or erasing process so as to increase a breakdown threshold of the transistor, and an inhibition voltage is applied to the gate or to a terminal of at least one floating-gate transistor connected to the transistor having its breakdown threshold increased to inhibit a phenomenon of soft programming or soft erase of the floating-gate transistor.
摘要翻译：本发明涉及一种编程或擦除存储单元的方法，该存储单元包括连接到浮栅晶体管的选择晶体管。根据该方法，将非零补偿电压施加到不参与编程或擦除处理的晶体管的栅极，以增加晶体管的击穿阈值，并且将抑制电压施加到栅极或栅极连接到具有其击穿阈值的晶体管的至少一个浮栅晶体管的端子增加以抑制浮动栅极晶体管的软编程或软擦除现象。

9. 发明授权

US06934192B2 EEPROM memory protected against the effects from a breakdown of an access transistor 有权
标题翻译： EEPROM存储器可防止存取晶体管故障的影响
公开(公告)号：US06934192B2
公开(公告)日：2005-08-23
申请号：US10178796
申请日：2002-06-24
申请人： François Tailliet , Francesco La Rosa
发明人： François Tailliet , Francesco La Rosa
IPC分类号： G11C16/04 , G11C16/08 , G11C16/10
CPC分类号： G11C16/10 , G11C16/0433 , G11C16/08
摘要： An electrically programmable and erasable memory includes memory cells, with each memory cell including a floating gate transistor and an access transistor. The floating gate transistor has a first terminal connected to the access transistor. The memory includes circuitry for respectively applying during an erasing phase a first signal, and a second signal on the control gate and on a second terminal of the floating gate transistors of the memory cells to be erased. The circuitry also applies to the gates of the corresponding access transistors of the memory cells to be erased a signal having a voltage that is different from a voltage of the first signal and has a low or zero potential difference with respect to a voltage of the second signal. The memory is protected against the effects from a breakdown of the gate oxide of an access transistor.
摘要翻译：电可编程和可擦除存储器包括存储单元，其中每个存储单元包括浮栅晶体管和存取晶体管。浮栅晶体管具有连接到存取晶体管的第一端。存储器包括用于在擦除阶段期间分别施加第一信号的电路和在要擦除的存储器单元的控制栅极和浮置栅极晶体管的第二端子上的第二信号。该电路还适用于存储器单元的相应存取晶体管的栅极，以被擦除具有与第一信号的电压不同的电压的信号，并且相对于第二个电压的电压具有低或零电位差信号。保护存储器不受存取晶体管栅极氧化物击穿的影响。

10. 发明授权

US06897689B2 Programmable POR circuit with two switching thresholds 有权
标题翻译：具有两个切换阈值的可编程POR电路
公开(公告)号：US06897689B2
公开(公告)日：2005-05-24
申请号：US10641337
申请日：2003-08-14
申请人： Francesco La Rosa
发明人： Francesco La Rosa
IPC分类号： H03K17/22 , H03L7/00
CPC分类号： H03K17/223
摘要： A power on reset circuit (POR) includes a first reset circuit for delivering a first reset signal when a supply voltage of the POR circuit is between a first low threshold and a first high threshold, and a second reset circuit for delivering a second reset signal when the supply voltage is between a second low threshold and a second high threshold. The second high threshold is less than the first high threshold. The POR circuit further includes at least one electrically erasable and programmable non-volatile memory cell. A delivery circuit outputs the first reset signal or the second reset based upon whether the at least one electrically erasable and programmable non-volatile memory cell is in an erased or programmed state. The POR circuit has a threshold for outputting the first or second reset signal that is programmable according to the intended application.
摘要翻译：上电复位电路（POR）包括第一复位电路，用于当POR电路的电源电压处于第一低阈值和第一高阈值之间时传送第一复位信号;以及第二复位电路，用于传送第二复位信号当电源电压处于第二低阈值和第二高阈值之间时。第二个高阈值小于第一个高阈值。 POR电路还包括至少一个电可擦除和可编程的非易失性存储单元。输送电路基于所述至少一个电可擦除可编程非易失性存储单元是否处于擦除或编程状态来输出第一复位信号或第二复位。 POR电路具有用于输出根据预期应用可编程的第一或第二复位信号的阈值。

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