专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07962543B2 Division with rectangular multiplier supporting multiple precisions and operand types 有权
标题翻译：具有矩形乘法器的分支，支持多种精度和操作数类型
公开(公告)号：US07962543B2
公开(公告)日：2011-06-14
申请号：US11756885
申请日：2007-06-01
申请人： Michael J. Schulte , Carl E. Lemonds, Jr. , Dimitri Tan
发明人： Michael J. Schulte , Carl E. Lemonds, Jr. , Dimitri Tan
IPC分类号： G06F7/535
CPC分类号： G06F7/4873 , G06F2207/5356
摘要： A division method includes determining a precision indicator for the division operation that indicates whether the quotient should be a single precision, double precision, or extended precision floating-point number. The division is performed at a rectangular multiplier using the Goldschmidt or Newton-Raphson algorithm. Each algorithm calculates one or more intermediate values in order to determine the quotient. For example, the Goldschmidt algorithm calculates a complement of a product of the dividend and an estimate of the reciprocal of the divisor. The quotient is determined based on a portion of one or more of these intermediate values. Because only a portion of the intermediate value is used, the division can be performed efficiently at the rectangular multiplier, and therefore the quotient can be determined more quickly and still achieve the desired level of precision.
摘要翻译：分割方法包括确定用于指示商是否应当是单精度，双精度或扩展精度浮点数的除法运算的精度指示符。使用Goldschmidt或Newton-Raphson算法在矩形乘法器上执行除法。每个算法计算一个或多个中间值以确定商。例如，Goldschmidt算法计算股息的乘积的互补和除数的倒数的估计。基于这些中间值中的一个或多个的一部分来确定商。因为仅使用中间值的一部分，所以可以在矩形乘法器上有效地执行除法，因此可以更快速地确定商并且仍然达到期望的精度水平。

2. 发明申请

US20080301213A1 DIVISION WITH RECTANGULAR MULTIPLIER SUPPORTING MULTIPLE PRECISIONS AND OPERAND TYPES 有权
标题翻译：具有矩形多用户支持多种精度和操作类型的部分
公开(公告)号：US20080301213A1
公开(公告)日：2008-12-04
申请号：US11756885
申请日：2007-06-01
申请人： Michael J. Schulte , Carl E. Lemonds, JR. , Dimitri Tan
发明人： Michael J. Schulte , Carl E. Lemonds, JR. , Dimitri Tan
IPC分类号： G06F7/483
CPC分类号： G06F7/4873 , G06F2207/5356
摘要： A division method includes determining a precision indicator for the division operation that indicates whether the quotient should be a single precision, double precision, or extended precision floating-point number. The division is performed at a rectangular multiplier using the Goldschmidt or Newton-Raphson algorithm. Each algorithm calculates one or more intermediate values in order to determine the quotient. For example, the Goldschmidt algorithm calculates a complement of a product of the dividend and an estimate of the reciprocal of the divisor. The quotient is determined based on a portion of one or more of these intermediate values. Because only a portion of the intermediate value is used, the division can be performed efficiently at the rectangular multiplier, and therefore the quotient can be determined more quickly and still achieve the desired level of precision.
摘要翻译：分割方法包括确定用于指示商是否应当是单精度，双精度或扩展精度浮点数的除法运算的精度指示符。使用Goldschmidt或Newton-Raphson算法在矩形乘法器上执行除法。每个算法计算一个或多个中间值以确定商。例如，Goldschmidt算法计算股息的乘积的互补和除数的倒数的估计。基于这些中间值中的一个或多个的一部分来确定商。因为仅使用中间值的一部分，所以可以在矩形乘法器上有效地执行除法，因此可以更快速地确定商并且仍然达到期望的精度水平。

3. 发明申请

US20130086357A1 STAGGERED READ OPERATIONS FOR MULTIPLE OPERAND INSTRUCTIONS 有权
标题翻译：对多种操作说明进行分类阅读操作
公开(公告)号：US20130086357A1
公开(公告)日：2013-04-04
申请号：US13248843
申请日：2011-09-29
申请人： Jeffrey P. Rupley , Dimitri Tan
发明人： Jeffrey P. Rupley , Dimitri Tan
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/30141 , G06F9/30098 , G06F9/3824
摘要： A central processing unit includes a register file having a plurality of read ports, a first execution unit having a first plurality of input ports, and logic operable to selectively couple different arrangements of the read ports to the input ports. A method for reading operands from a register file having a plurality of read ports by a first execution unit having a first plurality of input ports includes scheduling an instruction for execution by the first execution unit and selectively coupling a particular arrangement of the read ports to the input ports based on a type of the instruction.
摘要翻译：中央处理单元包括具有多个读取端口的寄存器文件，具有第一多个输入端口的第一执行单元和可操作以将读取端口的不同布置选择性地耦合到输入端口的逻辑。一种通过具有第一多个输入端口的第一执行单元从具有多个读取端口的寄存器文件读取操作数的方法，包括：调度由第一执行单元执行的指令，并选择性地将读取端口的特定布置耦合到基于指令类型的输入端口。

4. 发明授权

US09430237B2 Sharing register file read ports for multiple operand instructions 有权
标题翻译：共享寄存器文件读取端口用于多个操作数指令
公开(公告)号：US09430237B2
公开(公告)日：2016-08-30
申请号：US13248843
申请日：2011-09-29
申请人： Jeffrey P. Rupley , Dimitri Tan
发明人： Jeffrey P. Rupley , Dimitri Tan
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30141 , G06F9/30098 , G06F9/3824
摘要： A central processing unit includes a register file having a plurality of read ports, a first execution unit having a first plurality of input ports, and logic operable to selectively couple different arrangements of the read ports to the input ports. A method for reading operands from a register file having a plurality of read ports by a first execution unit having a first plurality of input ports includes scheduling an instruction for execution by the first execution unit and selectively coupling a particular arrangement of the read ports to the input ports based on a type of the instruction.
摘要翻译：中央处理单元包括具有多个读取端口的寄存器文件，具有第一多个输入端口的第一执行单元和可操作以将读取端口的不同布置选择性地耦合到输入端口的逻辑。一种通过具有第一多个输入端口的第一执行单元从具有多个读取端口的寄存器文件读取操作数的方法，包括：调度由第一执行单元执行的指令，并选择性地将读取端口的特定布置耦合到基于指令类型的输入端口。

5. 发明授权

US07698353B2 Floating point normalization and denormalization 有权
标题翻译：浮点归一化和非正规化
公开(公告)号：US07698353B2
公开(公告)日：2010-04-13
申请号：US11226040
申请日：2005-09-14
申请人： Dimitri Tan , Trinh H. Nguyen
发明人： Dimitri Tan , Trinh H. Nguyen
IPC分类号： G06F7/00
CPC分类号： G06F7/49936
摘要： A data processor includes a first bit field of a first plurality of bits representing a mantissa of a floating point number and a second bit field of a second plurality of bits representing an exponent of the floating point number. The first plurality of bits is partitioned into a plurality of regions, each of the plurality of regions comprises more than one bit of the first plurality of bits. A leading zero anticipator or other type of leading bit indication circuit is coupled to each region and determines a position of a leading bit of the first plurality of bits. A normalizer is coupled to receive a region of the plurality of regions that contains the leading bit, the normalizer may normalize or denormalize the region to produce a normalized or denormalized floating point number.
摘要翻译：数据处理器包括表示浮点数的尾数的第一多个比特的第一比特字段和表示浮点数的指数的第二多个比特的第二比特字段。第一多个比特被划分成多个区域，多个区域中的每一个包括第一多个比特的多于一个比特。前导零预测器或其他类型的引导位指示电路耦合到每个区域并确定第一多个位的前导位的位置。归一化器被耦合以接收包含前导位的多个区域的区域，归一化器可以对区域进行归一化或非归一化以产生归一化或非归一化浮点数。

6. 发明申请

US20070061391A1 Floating point normalization and denormalization 有权
标题翻译：浮点归一化和非正规化
公开(公告)号：US20070061391A1
公开(公告)日：2007-03-15
申请号：US11226040
申请日：2005-09-14
申请人： Dimitri Tan , Trinh Nguyen
发明人： Dimitri Tan , Trinh Nguyen
IPC分类号： G06F7/38
CPC分类号： G06F7/49936
摘要： A data processor includes a first bit field of a first plurality of bits representing a mantissa of a floating point number and a second bit field of a second plurality of bits representing an exponent of the floating point number. The first plurality of bits is partitioned into a plurality of regions, each of the plurality of regions comprises more than one bit of the first plurality of bits. A leading zero anticipator or other type of leading bit indication circuit is coupled to each region and determines a position of a leading bit of the first plurality of bits. A normalizer is coupled to receive a region of the plurality of regions that contains the leading bit, the normalizer may normalize or denormalize the region to produce a normalized or denormalized floating point number.
摘要翻译：数据处理器包括表示浮点数的尾数的第一多个比特的第一比特字段和表示浮点数的指数的第二多个比特的第二比特字段。第一多个比特被划分成多个区域，多个区域中的每一个包括第一多个比特的多于一个比特。前导零预测器或其他类型的引导位指示电路耦合到每个区域并确定第一多个位的前导位的位置。归一化器被耦合以接收包含前导位的多个区域的区域，归一化器可以对区域进行归一化或非归一化以产生归一化或非归一化浮点数。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式