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1. 发明授权

US08725786B2 Approximate SRT division method 有权
标题翻译：近似SRT分割法
公开(公告)号：US08725786B2
公开(公告)日：2014-05-13
申请号：US12770197
申请日：2010-04-29
申请人： Makia Powell
发明人： Makia Powell
IPC分类号： G06F7/44 , G06F7/52
CPC分类号： G06F7/5375 , G06F7/487 , G06F2207/5351 , G06F2207/5356
摘要： The invention relates to a program storage device readable by a machine, tangibly embodying a program of instructions executable by a specific semiconductor-based computational device situated in the machine to perform the steps of a partial SRT (PSRT) division of a dividend X by a divisor D to obtain a quotient Q. The steps include: causing a computer to obtain the dividend X and the divisor D; representing the dividend X and the divisor D as a digital representation having a plurality of bits; and performing iteratively a series of steps until a desired accuracy of the quotient Q is achieved. The invention also relates to an article of manufacture including a computer usable medium having computer readable program code embodied therein for causing a partial SRT (PSRT) division of a dividend X by a divisor D to generate a quotient Q.
摘要翻译：本发明涉及一种可由机器读取的程序存储设备，其有形地体现了可由位于机器中的特定的基于半导体的计算设备执行的指令程序，以执行以下步骤：将红利X的部分SRT（PSRT）划分为除数D获得商Q.步骤包括：使计算机获得股息X和除数D; 将分红X和除数D表示为具有多个比特的数字表示; 并且迭代地执行一系列步骤，直到达到商Q的期望精度。本发明还涉及一种制品，其包括具有计算机可读程序代码的计算机可用介质，该计算机可用介质包含在其中，用于通过除数D对乘数X进行部分SRT（PSRT）除法以产生商Q。

2. 发明授权

US5249149A Method and apparatus for performining floating point division 失效
标题翻译：执行浮点除法的方法和装置
公开(公告)号：US5249149A
公开(公告)日：1993-09-28
申请号：US755588
申请日：1991-09-03
申请人： Daniel Cocanougher , Peter W. Markstein
发明人： Daniel Cocanougher , Peter W. Markstein
IPC分类号： G06F7/52 , G06F7/535
CPC分类号： G06F7/535 , G06F2207/5351 , G06F2207/5355 , G06F2207/5356 , G06F7/4873 , G06F7/49957
摘要： A method for performing floating point division is provided for producing a quotient having a mantissa of n bits. The method consists of the steps of accessing an initial guess of a reciprocal of the divisor from a table of divisor reciprocals, computing an initial estimate the quotient in a corresponding estimate from the initial estimate of the reciprocal, increasing the precision of the mantissa of the reciprocal estimate, quotient estimate, and remainder estimate by computing an error parameter and iteratively computing a current reciprocal estimate, a current quotient estimate and a current remainder estimate from the error parameter and the latest reciprocal estimate, quotient estimate and remainder estimates. Also, the step of increasing the precision is repeated until the quotient estimate and reciprocal estimate exceed n bits. Lastly, the final quotient is computed from the last current quotient estimate plus the last current reciprocal estimate times the last current remainder estimate. A floating point apparatus is also provided that implements the floating point division method. The application of this method and apparatus provide a quotient result that is correctly rounded without conditionally testing the magnitude of the quotient.
摘要翻译：提供了一种用于执行浮点除法的方法，用于产生具有n位尾数的商。该方法包括以下步骤：从除数倒数表中获取除数的倒数的初始猜测，从相对估计的初始估计中计算相应估计中的商的初始估计，从而增加尾数尾数的精度通过计算误差参数并迭代地计算来自误差参数和最新的倒数估计，商估计和余数估计的当前倒数估计值，当前商估计值和当前剩余估计值，进行估计，商估计和剩余估计。此外，重复提高精度的步骤，直到商估计和倒数估计超过n位。最后，最后的商是从最后一个当前商估计加上最后的当前的倒数估计乘以最后的当前剩余估计来计算的。还提供了实现浮点分割方法的浮点装置。该方法和装置的应用提供了正确四舍五入的商结果，而无需有条件地测试商的幅度。

3. 发明申请

US20100281087A1 APPROXIMATE SRT DIVISION METHOD 有权
标题翻译：近似SRT方法
公开(公告)号：US20100281087A1
公开(公告)日：2010-11-04
申请号：US12770197
申请日：2010-04-29
申请人： Makia Powell
发明人： Makia Powell
IPC分类号： G06F7/487 , G06F5/01
CPC分类号： G06F7/5375 , G06F7/487 , G06F2207/5351 , G06F2207/5356
摘要： The invention relates to a program storage device readable by a machine, tangibly embodying a program of instructions executable by a specific semiconductor-based computational device situated in the machine to perform the steps of a partial SRT (PSRT) division of a dividend X by a divisor D to obtain a quotient Q. The steps include: causing a computer to obtain the dividend X and the divisor D; representing the dividend X and the divisor D as a digital representation having a plurality of bits; and performing iteratively a series of steps until a desired accuracy of the quotient Q is achieved. The invention also relates to an article of manufacture including a computer usable medium having computer readable program code embodied therein for causing a partial SRT (PSRT) division of a dividend X by a divisor D to generate a quotient Q.
摘要翻译：本发明涉及一种可由机器读取的程序存储设备，其有形地体现了可由位于机器中的特定的基于半导体的计算设备执行的指令程序，以执行以下步骤：将红利X的部分SRT（PSRT）划分为除数D获得商Q.步骤包括：使计算机获得股息X和除数D; 将分红X和除数D表示为具有多个比特的数字表示; 并且迭代地执行一系列步骤，直到达到商Q的期望精度。本发明还涉及一种制品，其包括具有计算机可读程序代码的计算机可用介质，该计算机可用介质包含在其中，用于通过除数D对乘数X进行部分SRT（PSRT）除法以产生商Q。

4. 发明授权

US4707798A Method and apparatus for division using interpolation approximation 失效
标题翻译：使用插值近似分割的方法和装置
公开(公告)号：US4707798A
公开(公告)日：1987-11-17
申请号：US687912
申请日：1984-12-31
申请人： Hiraku Nakano
发明人： Hiraku Nakano
IPC分类号： G06F1/035 , G06F7/483 , G06F7/52 , G06F7/535 , G06F17/17
CPC分类号： G06F7/535 , G06F1/0356 , G06F2101/12 , G06F2207/5351 , G06F2207/5352 , G06F2207/5354 , G06F2207/5356
摘要： A divide method and a divide apparatus for use in a data processing system. The divisor and dividend are normalized in a normalization circuit. A table unit stores a plurality of approximate reciprocal divisors and differences between adjacent approximate reciprocal divisors and is addressed by the high-order bits of the normalized divisor. The approximate reciprocal divisor read out from the table unit is, in an interpolation approximation circuit, changed into an interpolation approximated approximate reciprocal divisor in accordance with a plurality of bits following the high-order bits and the difference. A multiplication unit multiplies the interpolation approximated approximate reciprocal divisor by the normalized dividend to output a quotient.
摘要翻译：一种用于数据处理系统的分频方法和分频装置。除数和除数在归一化电路中归一化。表单元存储多个近似倒数因子和相邻近似倒数因子之间的差异，并通过归一化除数的高位来寻址。从表格单元读出的近似互易除数在内插近似电路中根据高位位之后的多个位和差值而变为内插近似近似互易除数。乘法单元将内插近似近似互易除数乘以归一化余数以输出商。

5. 发明授权

US4337519A Multiple/divide unit 失效
标题翻译：多/除单位
公开(公告)号：US4337519A
公开(公告)日：1982-06-29
申请号：US115619
申请日：1980-01-28
申请人： Tetsunori Nishimoto
发明人： Tetsunori Nishimoto
IPC分类号： G06F7/52 , G06F7/535 , G06F7/544 , G06F7/48
CPC分类号： G06F7/544 , G06F7/523 , G06F7/535 , G06F7/5375 , G06F2207/5351
摘要： An arithmetic unit which enables speedup of operation in a system for division and/or multiplication by setting specific logical conditions for a decoder. Such specific logical conditions allows elimination of adding means which are essential in known arithmetic units to constitute the division and multiplication system in combination with the decoder.
摘要翻译：一种算术单元，其通过为解码器设定特定的逻辑条件，能够加速系统中的运算，进行分频和/或乘法运算。这样的特定逻辑条件允许消除在已知运算单元中必不可少的加法装置，以与解码器结合构成除法和乘法系统。

6. 发明授权

US08655937B1 High precision integer division using low precision hardware operations and rounding techniques 有权
标题翻译：使用低精度硬件操作和舍入技术的高精度整数除法
公开(公告)号：US08655937B1
公开(公告)日：2014-02-18
申请号：US12432064
申请日：2009-04-29
申请人： Julius Vanderspek
发明人： Julius Vanderspek
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F7/4873 , G06F2207/5351
摘要： One or more embodiments of the invention set forth techniques to perform integer division using a floating point hardware unit supporting floating point variables of a certain bit size. The numerator and denominator are integers having a bit size that is greater than the bit size of the floating point variables supported by the floating point hardware unit. Error correcting techniques are utilized to account for any loss of precision caused by the floating point operations.
摘要翻译：本发明的一个或多个实施例提出了使用支持某一位大小的浮点变量的浮点硬件单元执行整数除法的技术。分子和分母是具有大于浮点硬件单元支持的浮点变量的位大小的位大小的整数。利用纠错技术来解释由浮点运算造成的任何精度损失。

7. 发明授权

US08140608B1 Pipelined integer division using floating-point reciprocal 有权
标题翻译：使用浮点互易的流水线整数除法
公开(公告)号：US08140608B1
公开(公告)日：2012-03-20
申请号：US11756188
申请日：2007-05-31
申请人： Norbert Juffa
发明人： Norbert Juffa
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F7/4873 , G06F2207/5351 , G06F2207/5356
摘要： One embodiment of the present invention sets forth a technique for performing fast integer division using commonly available arithmetic operations. The technique may be implemented in a two-stage process using a single-precision floating point reciprocal in conjunction with integer addition and multiplication. Furthermore, the technique may be fully pipelined on many conventional processors for performance that is comparable to the best available high-performance alternatives.
摘要翻译：本发明的一个实施例提出了一种使用常用的算术运算进行快速整数除法的技术。该技术可以在使用单精度浮点互易结合整数加法和乘法的两阶段过程中实现。此外，该技术可以在许多常规处理器上完全流水线化，以便与最佳可用的高性能替代方案相当。

8. 发明授权

US3828175A Method and apparatus for division employing table-lookup and functional iteration 失效
标题翻译：方法和装置使用表查找和功能迭代
公开(公告)号：US3828175A
公开(公告)日：1974-08-06
申请号：US30222372
申请日：1972-10-30
申请人： AMDAHL CORP
发明人： AMDAHL G , CLEMENTS M
IPC分类号： G02C1/06 , G06F7/52 , G06F7/535
CPC分类号： G06F7/535 , G06F2207/5351 , G06F2207/5352 , G06F2207/5355 , G06F2207/5356
摘要： Disclosed is a divide method and a divide apparatus for use in a data processing system. A given dividend, No, and a given divisor, Do, are used to calculate a quotient Q. The quotient Q consists of the quotient bytes Q(O), Q(l),...,Q(i), Q(i+l),..., Q(n-l). The quotient bytes Q(i) are formed in successive iterations of the equation
摘要翻译：公开了一种在数据处理系统中使用的分割方法和分割装置。给定的红利分配（No）和给定的除数（Do）被用于计算商Q.商Q由商字节Q（O），Q（1），...，Q（i），Q（ i + 1），...，Q（nl）。商数字节Q（i）在等式[Q（i）]（dp）+ r（i）= Q（i + 1），r（i + 1）WERE（DP）IS的连续迭代中形成 MULTIPLIER和R（I）是在从前一次迭代中Q（i）个字节进行传输之后的结果。迭代乘数（dp）等于1-（D）（Dp）<1>其中（Dp）<1>是近似互易除数。使用D的表查找近似，使用（Dp）的值大于D，并采用初始计算序列，从而确保在迭代中仅需要求和。

9. 发明授权

US09785407B2 Data processing apparatus having combined divide-square root circuitry 有权
公开(公告)号：US09785407B2
公开(公告)日：2017-10-10
申请号：US14549639
申请日：2014-11-21
申请人： ARM LIMITED
发明人： Neil Burgess , David Raymond Lutz
IPC分类号： G06F7/535 , G06F7/552 , G06F7/537 , G06F9/30
CPC分类号： G06F7/535 , G06F7/5375 , G06F7/5525 , G06F9/3001 , G06F2207/5351 , G06F2207/5528
摘要： A processing apparatus has combined divide-square root circuitry for performing a radix-N SRT divide algorithm and a radix-N SRT square root algorithm, where N is an integer power-of-2. The combined circuitry has shared remainder updating circuitry which performs remainder updates for a greater number of iterations per cycle for the SRT divide algorithm than for the SRT square root algorithm. This allows reduced circuit area while avoiding the SRT square root algorithm compromising the performance of the SRT divide algorithm.

10. 发明申请

US20170199723A1 CIRCUITRY AND METHOD FOR PERFORMING DIVISION 审中-公开
公开(公告)号：US20170199723A1
公开(公告)日：2017-07-13
申请号：US14994601
申请日：2016-01-13
申请人： ARM LIMITED
发明人： Javier Diaz BRUGUERA
IPC分类号： G06F7/491 , G06F7/487
CPC分类号： G06F7/487 , G06F7/4873 , G06F7/537 , G06F2207/5351
摘要： A data processing apparatus comprises signal receiving circuitry to receive a signal corresponding to a divide instruction that identifies a dividend x and a divisor d. Processing circuitry performs, in response to said divide instruction, a radix-N division algorithm to generate a result value q=x/d, where N is an integer power of 2 and greater than 1. Said division algorithm comprises a plurality of iterations, each of said plurality of iterations being performed by quotient digit calculation circuitry to determine a quotient value of that iteration q[i+1] based on a remainder value of a previous iteration rem[i]; and remainder calculation circuitry to determine a remainder value of that iteration rem[i+1] based on said quotient value of that iteration q[i+1] and said remainder value of said previous iteration rem[i]. Result calculation circuitry derives said result value q based on each quotient value selected by said digit selection circuitry for each of said plurality of iterations. For at least some of said plurality of iterations, said quotient digit calculation circuitry speculatively determines a set of candidate values before a quotient value of said previous iteration is known and, in response to said quotient value of said previous iteration becoming known, determines said quotient value of that iteration q[i+1] based on one of said candidate values.

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