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1. 发明授权

US08347310B1 System and method for representing and managing a multi-architecure co-processor application program 有权
标题翻译：用于表示和管理多架构协处理器应用程序的系统和方法
公开(公告)号：US08347310B1
公开(公告)日：2013-01-01
申请号：US11938750
申请日：2007-11-12
申请人： Julius Vanderspek , Nicholas Patrick Wilt , Jayant Kolhe , Ian A. Buck , Bastiaan Aarts
发明人： Julius Vanderspek , Nicholas Patrick Wilt , Jayant Kolhe , Ian A. Buck , Bastiaan Aarts
IPC分类号： G06F3/00 , G06F9/44
CPC分类号： G06F8/447
摘要： One embodiment of the present invention sets forth a technique for representing and managing a multi-architecture co-processor application program. Source code for co-processor functions is compiled in two stages. The first stage incorporates a majority of the computationally intensive processing steps associated with co-processor code compilation. The first stage generates virtual assembly code from the source code. The second stage generates co-processor machine code from the virtual assembly. Both the virtual assembly and co-processor machine code may be included within the co-processor enabled application program. A co-processor driver uses a description of the currently available co-processor to select between virtual assembly and co-processor machine code. If the virtual assembly code is selected, then the co-processor driver compiles the virtual assembly into machine code for the current co-processor.
摘要翻译：本发明的一个实施例提出了一种用于表示和管理多架构协处理器应用程序的技术。协处理器功能的源代码分两个阶段编译。第一阶段包含与协处理器代码编译相关联的大部分计算密集型处理步骤。第一阶段从源代码生成虚拟汇编代码。第二阶段从虚拟程序集中生成协处理器机器代码。虚拟装配和协处理器机器码都可以包括在支持协处理器的应用程序中。协处理器驱动程序使用当前可用的协处理器的描述来在虚拟装配和协处理器机器代码之间进行选择。如果选择了虚拟汇编代码，则协处理器驱动程序将虚拟程序集编译为当前协处理器的机器代码。

2. 发明授权

US08655937B1 High precision integer division using low precision hardware operations and rounding techniques 有权
标题翻译：使用低精度硬件操作和舍入技术的高精度整数除法
公开(公告)号：US08655937B1
公开(公告)日：2014-02-18
申请号：US12432064
申请日：2009-04-29
申请人： Julius Vanderspek
发明人： Julius Vanderspek
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F7/4873 , G06F2207/5351
摘要： One or more embodiments of the invention set forth techniques to perform integer division using a floating point hardware unit supporting floating point variables of a certain bit size. The numerator and denominator are integers having a bit size that is greater than the bit size of the floating point variables supported by the floating point hardware unit. Error correcting techniques are utilized to account for any loss of precision caused by the floating point operations.
摘要翻译：本发明的一个或多个实施例提出了使用支持某一位大小的浮点变量的浮点硬件单元执行整数除法的技术。分子和分母是具有大于浮点硬件单元支持的浮点变量的位大小的位大小的整数。利用纠错技术来解释由浮点运算造成的任何精度损失。

3. 发明授权

US08281294B1 System and method for representing and managing a multi-architecture co-processor application program 有权
标题翻译：用于表示和管理多架构协处理器应用程序的系统和方法
公开(公告)号：US08281294B1
公开(公告)日：2012-10-02
申请号：US11938755
申请日：2007-11-12
申请人： Julius Vanderspek , Nicholas Patrick Wilt , Jayant Kolhe , Ian A. Buck , Bastiaan Aarts
发明人： Julius Vanderspek , Nicholas Patrick Wilt , Jayant Kolhe , Ian A. Buck , Bastiaan Aarts
IPC分类号： G06F9/45
CPC分类号： G06F9/44547 , G06F8/447
摘要： One embodiment of the present invention sets forth a technique for representing and managing a multi-architecture co-processor application program. Source code for co-processor functions is compiled in two stages. The first stage incorporates a majority of the computationally intensive processing steps associated with co-processor code compilation. The first stage generates virtual assembly code from the source code. The second stage generates co-processor machine code from the virtual assembly. Both the virtual assembly and co-processor machine code may be included within the co-processor enabled application program. A co-processor driver uses a description of the currently available co-processor to select between virtual assembly and co-processor machine code. If the virtual assembly code is selected, then the co-processor driver compiles the virtual assembly into machine code for the current co-processor.
摘要翻译：本发明的一个实施例提出了一种用于表示和管理多架构协处理器应用程序的技术。协处理器功能的源代码分两个阶段编译。第一阶段包含与协处理器代码编译相关联的大部分计算密集型处理步骤。第一阶段从源代码生成虚拟汇编代码。第二阶段从虚拟程序集中生成协处理器机器代码。虚拟装配和协处理器机器码都可以包括在支持协处理器的应用程序中。协处理器驱动程序使用当前可用的协处理器的描述来在虚拟装配和协处理器机器代码之间进行选择。如果选择了虚拟汇编代码，则协处理器驱动程序将虚拟程序集编译为当前协处理器的机器代码。

4. 发明授权

US08276132B1 System and method for representing and managing a multi-architecture co-processor application program 有权
公开(公告)号：US08276132B1
公开(公告)日：2012-09-25
申请号：US11938747
申请日：2007-11-12
申请人： Julius Vanderspek , Nicholas Patrick Wilt , Jayant Kolhe , Ian A. Buck , Bastiaan Aarts
发明人： Julius Vanderspek , Nicholas Patrick Wilt , Jayant Kolhe , Ian A. Buck , Bastiaan Aarts
IPC分类号： G06F9/45
CPC分类号： G06F8/36 , G06F8/30 , G06F9/45516
摘要： One embodiment of the present invention sets forth a technique for representing and managing a multi-architecture co-processor application program. Source code for co-processor functions is compiled in two stages. The first stage incorporates a majority of the computationally intensive processing steps associated with co-processor code compilation. The first stage generates virtual assembly code from the source code. The second stage generates co-processor machine code from the virtual assembly. Both the virtual assembly and co-processor machine code may be included within the co-processor enabled application program. A co-processor driver uses a description of the currently available co-processor to select between virtual assembly and co-processor machine code. If the virtual assembly code is selected, then the co-processor driver compiles the virtual assembly into machine code for the current co-processor.

5. 发明授权

US08938485B1 Integer division using floating-point reciprocal 有权
标题翻译：整数除法使用浮点互易
公开(公告)号：US08938485B1
公开(公告)日：2015-01-20
申请号：US12030178
申请日：2008-02-12
申请人： Julius Vanderspek
发明人： Julius Vanderspek
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F2207/5351 , G06F2207/5352 , G06F2207/5356
摘要： One embodiment of the present invention sets forth a technique for performing fast integer division using commonly available arithmetic operations. The technique may be implemented in a four-stage process using a single-precision floating point reciprocal in conjunction with integer addition and multiplication. Furthermore, the technique may be fully pipelined on many conventional processors for overall performance that is comparable to the best available high-performance alternatives.
摘要翻译：本发明的一个实施例提出了一种使用常用的算术运算进行快速整数除法的技术。该技术可以在使用单精度浮点互易结合整数加法和乘法的四阶段过程中实现。此外，该技术可以在许多常规处理器上完全流水线化，以实现与最佳可用高性能替代方案相当的整体性能。

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