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1. 发明授权

US09501092B1 Systems and methods for clock alignment using pipeline stages 有权
标题翻译：使用流水线阶段进行时钟对准的系统和方法
公开(公告)号：US09501092B1
公开(公告)日：2016-11-22
申请号：US14974506
申请日：2015-12-18
申请人： Altera Corporation
发明人： Dana How , Carl Ebeling , Audrey Catherine Kertesz
IPC分类号： H03L7/06 , G06F1/12
CPC分类号： H04L7/02 , G06F1/12 , H04L7/0054
摘要： Systems and methods for phase detection are disclosed. A collapsible three-stage pipeline includes a first register in a first stage having a first clock signal having first clock edges, a second register in a second stage that receives a first signal from the first stage, and having a second clock signal having second clock edges, and a third register in a third stage that receives a second signal from the second stage, and having a third clock signal having third clock edges, wherein each second clock edge has a corresponding first clock edge and a corresponding third clock edge. The circuitry may further include a two-stage pipeline including fourth and fifth stages, a counter that provides an input signal into the collapsible three-stage pipeline and the two-stage pipeline, and a comparator that compares a first output of the collapsible three-stage pipeline and a second output of the two-stage pipeline.
摘要翻译：公开了用于相位检测的系统和方法。可折叠三级流水线包括第一级中的第一寄存器，其具有具有第一时钟沿的第一时钟信号，第二级中的第二寄存器，其接收来自第一级的第一信号，并具有第二时钟信号，该第二时钟信号具有第二时钟边缘和第三寄存器，其接收来自第二级的第二信号，并具有具有第三时钟沿的第三时钟信号，其中每个第二时钟沿具有对应的第一时钟沿和对应的第三时钟沿。该电路还可以包括一个包括第四和第五级的两级流水线，一个向可折叠的三级流水线和两级流水线提供输入信号的计数器，以及比较器，阶段管道和二级管道的第二输出。

2. 发明申请

US20220224656A1 PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP 有权
公开(公告)号：US20220224656A1
公开(公告)日：2022-07-14
申请号：US17690994
申请日：2022-03-09
申请人： Altera Corporation
发明人： Michael David Hutton , Herman Henry Schmit , Dana How
IPC分类号： H04L49/109 , G06F15/78 , H04L41/0893 , H04L41/12 , H04L47/80
摘要： Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.

3. 发明申请

US20190327176A1 NETWORK-ON-CHIP WITH FIXED AND CONFIGURABLE FUNCTIONS 审中-公开
公开(公告)号：US20190327176A1
公开(公告)日：2019-10-24
申请号：US16456372
申请日：2019-06-28
申请人： Altera Corporation
发明人： Dana How , Herman Henry Schmit , Sean R. Atsatt
IPC分类号： H04L12/851 , H04L12/26 , H04L12/24
摘要： Systems and methods are provided herein for providing an NoC including a configurable array of nodes, where a node of the configurable array of nodes operates in a default operating mode until a replacement operating mode is triggered. For example, when an NoC is unconfigured, a latch bank may be initialized to “clear,” such that no routing decisions are stored. This may enable a default operating mode where routing logic updates the latches' values as needed to implement required routing behavior in a dynamic fashion until configuration is performed.

4. 发明授权

US10367756B2 Programmable logic device with integrated network-on-chip 有权
公开(公告)号：US10367756B2
公开(公告)日：2019-07-30
申请号：US15298122
申请日：2016-10-19
申请人： Altera Corporation
发明人： Michael David Hutton , Herman Henry Schmit , Dana How
IPC分类号： H04L12/933 , G06F15/78 , H04L12/24 , H04L12/927
摘要： Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.

5. 发明授权

US10082541B2 Mixed redundancy scheme for inter-die interconnects in a multichip package 有权
公开(公告)号：US10082541B2
公开(公告)日：2018-09-25
申请号：US14737246
申请日：2015-06-11
申请人： Altera Corporation
发明人： Dana How , Dinesh Patil , Arifur Rahman , Jeffrey Erik Schulz
IPC分类号： G06F13/00 , G06F13/20 , G06F3/00 , G01R31/3185 , G01R31/28 , H01L25/065 , G06F11/16 , G06F11/18 , G06F11/20 , G06F11/00
摘要： Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.

6. 发明授权

US09588176B1 Techniques for using scan storage circuits 有权
标题翻译：使用扫描存储电路的技术
公开(公告)号：US09588176B1
公开(公告)日：2017-03-07
申请号：US14610341
申请日：2015-01-30
申请人： Altera Corporation
发明人： Michael Hutton , Sean Atsatt , James Ball , Dana How , Jeffrey Chromczak , Eng Ling Ho
IPC分类号： G01R31/28 , G01R31/3177
CPC分类号： G01R31/3177 , G11C29/32
摘要： An integrated circuit may include user storage circuits and scan storage circuits. The scan storage circuits may store data from the user storage circuits and provide the data to a user interface during a read-back operation. The user storage circuits may store data from the scan storage circuits, which the scan storage circuits may have received from the user interface during a write-back operation. The scan storage circuits may be arranged in a scan chain and controlled by a local control circuit. The integrated circuit may include multiple local control circuits that each control a sector of the integrated circuit. The local control circuits may communicate with a global control circuit over a communication network, and the global control circuit may communicate with the user interface.
摘要翻译：集成电路可以包括用户存储电路和扫描存储电路。扫描存储电路可以存储来自用户存储电路的数据，并且在回读操作期间将数据提供给用户界面。用户存储电路可以在回写操作期间存储来自扫描存储电路的扫描存储电路的数据，扫描存储电路可能从用户界面接收。扫描存储电路可以布置在扫描链中并由本地控制电路控制。集成电路可以包括多个本地控制电路，每个本地控制电路控制集成电路的扇区。本地控制电路可以通过通信网络与全局控制电路进行通信，并且全局控制电路可以与用户界面进行通信。

7. 发明申请

US20160363626A1 MIXED REDUNDANCY SCHEME FOR INTER-DIE INTERCONNECTS IN A MULTICHIP PACKAGE 审中-公开
标题翻译：混合冗余方案用于多媒体包中的互连互连
公开(公告)号：US20160363626A1
公开(公告)日：2016-12-15
申请号：US14737246
申请日：2015-06-11
申请人： Altera Corporation
发明人： Dana How , Dinesh Patil , Arifur Rahman , Jeffrey Erik Schulz
IPC分类号： G01R31/3185 , G01R31/28 , H01L25/065
CPC分类号： G01R31/318597 , G01R31/2896 , G06F11/00 , G06F11/1625 , G06F11/186 , G06F11/2007 , H01L25/0652 , H01L2225/06527
摘要： Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.
摘要翻译：提供了具有多个集成电路管芯的集成电路封装。多芯片封装可以包括通过晶片间封装互连耦合到一个或多个从裸片的主裸片。可以实施混合（即，主动和被动）互连冗余方案以帮助修复潜在的故障互连以提高组装产量。携带正常用户信号的互连可以使用主动冗余方案通过在必要时选择性地切换到使用备用驱动器块来修复。另一方面，可以使用无源冗余方案来支持携带上电复位信号，初始化信号和用于同步主器件和从器件之间的操作的其他关键控制信号的互连，通过使用两个或更多个复制线来为每个关键信号。

8. 发明授权

US09503057B1 Clock grid for integrated circuit 有权
标题翻译：集成电路的时钟网格
公开(公告)号：US09503057B1
公开(公告)日：2016-11-22
申请号：US14137086
申请日：2013-12-20
申请人： Altera Corporation
发明人： Ramanand Venkata , Dana How , Christopher Lane
IPC分类号： G06F1/04 , H03K3/01 , H03K5/159
CPC分类号： H03L7/0807 , G06F1/10 , H03K3/01 , H03K5/159 , H03K19/1774 , H03K2005/00019 , H03L7/0812
摘要： Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one or more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.
摘要翻译：系统和方法用于在集成电路上分配时钟或其他信号。在一些方面，一个或多个分布式的偏移对象被配置用于减少或消除偏斜，同时将多个时钟分配段链接成任意形状和大小的一个时钟树。

9. 发明申请

US20160049941A1 PROGRAMMABLE CIRCUIT HAVING MULTIPLE SECTORS 审中-公开
标题翻译：具有多个部门的可编程电路
公开(公告)号：US20160049941A1
公开(公告)日：2016-02-18
申请号：US14460548
申请日：2014-08-15
申请人： Altera Corporation
发明人： Dana How , Sean R. Atsatt , Michael David Hutton , Herman Henry Schmit
IPC分类号： H03K19/177 , H03K19/007
摘要： Systems and methods relating to a programmable circuit. The programmable circuit includes multiple sectors. Each sector includes configurable functional blocks, configurable routing wires, configuration bits for storing configurations for the functional blocks and routing wires, and local control circuitry for interfacing with the configuration bits to configure the sector. The programmable circuit may include global control circuitry for interfacing with the local control circuitry to configure the sector. Each sector may be independently operable and/or operable in parallel with other sectors. Operating the programmable circuit may include using the local control circuitry to interface with the configurations bit and configure the sector. Additionally, operating the programmable circuit may include using the global control circuitry to interface with respective local control circuitry and configure the sector.
摘要翻译：与可编程电路相关的系统和方法。可编程电路包括多个扇区。每个扇区包括可配置的功能块，可配置的布线，用于存储功能块和布线的配置的配置位，以及用于与配置位对接以配置扇区的本地控制电路。可编程电路可以包括用于与本地控制电路接口配置该扇区的全局控制电路。每个扇区可以独立地可操作和/或与其他扇区并行操作。操作可编程电路可以包括使用本地控制电路与配置位进行接口并配置扇区。另外，操作可编程电路可以包括使用全局控制电路与相应的本地控制电路进行接口并配置该扇区。

10. 发明授权

US10367745B1 Network-on-chip with fixed and configurable functions 有权
公开(公告)号：US10367745B1
公开(公告)日：2019-07-30
申请号：US15390033
申请日：2016-12-23
申请人： Altera Corporation
发明人： Dana How , Herman Henry Schmit , Sean R. Atsatt
IPC分类号： H04L12/50 , H04L12/851 , H04L12/26 , H04L12/24
摘要： Systems and methods are provided herein for providing an NoC including a configurable array of nodes, where a node of the configurable array of nodes operates in a default operating mode until a replacement operating mode is triggered. For example, when an NoC is unconfigured, a latch bank may be initialized to “clear,” such that no routing decisions are stored. This may enable a default operating mode where routing logic updates the latches' values as needed to implement required routing behavior in a dynamic fashion until configuration is performed.

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