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1. 发明授权

US4994993A System for detecting and correcting errors generated by arithmetic logic units 失效
标题翻译：用于检测和校正由算术逻辑单元产生的错误的系统
公开(公告)号：US4994993A
公开(公告)日：1991-02-19
申请号：US262658
申请日：1988-10-25
申请人： Safdar M. Asghar , John G. Bartkowiak , Eric A. Suss
发明人： Safdar M. Asghar , John G. Bartkowiak , Eric A. Suss
IPC分类号： G06F11/00 , G06F11/10 , G06F11/14
CPC分类号： G06F11/1497 , G06F11/104
摘要： Apparatus is provided for performing a method for detecting and correcting errors in one clock cycle that occur during arithmetic operations of at least two operands. Specifically, two operands are operated on to obtain a result. The digits of the result are added to one another. This adding step is repeated until a first single digit is achieved. The digits of each of the operands are added to one another to obtain an intermediate sum. The digits of the intermediate sum, in turn, are added to one another. Once again, this operation is repeated until a second single digit is achieved. The first single digit number is compared with the second single digit number and a signal indicative of error is generated if the comparison is unsuccessful.In order to correct the error, the digits of each of the operands are added to one another to obtain an intermediate sum. Sequentially, a digit is subtracted from the partial sum of the remaining digits of each of the operands. The results of the subtraction for each operand are added to one another at the end of each sequential cycle to obtain a set of arguments, each of which is subtracted from the intermediate sum to obtain a set of partial differences. The partial differences are concatenated to obtain a transitional value. By eliminating certain digits, a correct value of the arithmetic operation is obtained.

2. 发明授权

US5347480A Digital signal processing apparatus 失效
标题翻译：数字信号处理装置
公开(公告)号：US5347480A
公开(公告)日：1994-09-13
申请号：US53959
申请日：1993-04-27
申请人： Safdar M. Asghar , John G. Bartkowiak , Michael A. Nix
发明人： Safdar M. Asghar , John G. Bartkowiak , Michael A. Nix
IPC分类号： G06F7/52 , G06F7/523 , G06F7/53 , G06F7/544 , G06F9/302 , G06F9/318 , G06F17/10 , G06F15/00
CPC分类号： G06F17/10 , G06F7/5443 , G06F9/30014 , G06F9/30167 , G06F9/30181
摘要： An apparatus for processing a received signal according to a digital signal processing algorithm having a multiplier and a limit and quantization circuit appropriately connected within the apparatus to permit operation of the multiplier and the limit and quantization circuit in parallel with logic processing by the apparatus. The address bus system of the apparatus is connected to the parallel-connected components and conveys instructions to the parallel-connected components, at least in part, by predetermined address information via the address bus system.
摘要翻译：一种用于根据数字信号处理算法处理接收信号的装置，该数字信号处理算法具有在装置内适当连接的乘法器和限制量化电路，以允许乘法器和极限量化电路与该装置的逻辑处理并行进行操作。该设备的地址总线系统连接到并联连接的组件，并且至少部分地通过地址总线系统通过预定的地址信息将指令传送到并联连接的组件。

3. 发明授权

US4994801A Apparatus adaptable for use in effecting communications between an analog device and a digital device 失效
标题翻译：适用于实现模拟设备和数字设备之间的通信的设备
公开(公告)号：US4994801A
公开(公告)日：1991-02-19
申请号：US428614
申请日：1989-10-30
申请人： Safdar M. Asghar , John G. Bartkowiak , Miki Z. Moyal
发明人： Safdar M. Asghar , John G. Bartkowiak , Miki Z. Moyal
IPC分类号： H03H17/06
CPC分类号： H03H17/0444 , H03H17/0621 , H03H17/0664
摘要： An apparatus adaptable for use in effecting communications between an analog device and a digital device, having an analog-digital-analog circuit for converting incoming analog signals received from the analog device to incoming digital signals, and for converting interpolated outgoing digital signals to outgoing analog signals. The apparatus further has a digital signal processing circuit for decimating the incoming digital signals and providing a decimated incoming digital signal to the digital device, and for interpolating outgoing digital signals received from the digital device and providing an interpolated outgoing digital signal to the analog-digital-analog device. The analog-digital-analog device includes a single digital-to-analog converter and switches for selectively configuring the analog-digital-analog circuit to effect conversion of incoming analog signals to incoming digital signals or, alternatively, to effect conversion of interpolated outgoing digital signals to outgoing analog signals. The digital signal processing circuit is comprised of a plurality of modules which are configured so that a specified set of the plurality of modules effects a specified number of iterations of decimation and a specified number of iterations of interpolation. Certain of the specified set of modules participate in both the decimation and interpolation operations. The modules are further designed so that additional modules may be added to the specified set of modules to increase the iterations of decimation or to increase the iterations of interpolation, or to increase the iterations of both decimation and interpolation.
摘要翻译：一种适于用于实现模拟设备和数字设备之间的通信的设备，具有用于将从模拟设备接收的输入模拟信号转换为输入数字信号的模拟数字模拟电路，以及用于将内插输出数字信号转换为输出模拟信号。该装置还具有数字信号处理电路，用于抽取输入的数字信号并向数字装置提供抽取的输入数字信号，并且用于内插从数字装置接收到的输出数字信号，并将内插的输出数字信号提供给模拟数字 -analog设备。模拟数字模拟设备包括单个数模转换器和开关，用于选择性地配置模拟数字模拟电路以实现输入模拟信号到输入数字信号的转换，或者替代地，实现内插输出数字信号输出模拟信号。数字信号处理电路包括多个模块，其被配置为使得多个模块的指定集合实现特定数量的抽取迭代次数和指定次数的内插迭代。指定的一组模块中的某些参与抽取和插值操作。这些模块被进一步设计，使得附加的模块可以被添加到指定的模块集合中，以增加抽取的迭代或增加内插的迭代，或增加抽取和插值的迭代。

4. 发明授权

US06230255B1 Communications processor for voice band telecommunications 失效
标题翻译：通讯处理器用于语音频段电讯
公开(公告)号：US06230255B1
公开(公告)日：2001-05-08
申请号：US07548709
申请日：1990-07-06
申请人： Safdar M. Asghar , John G. Bartkowiak
发明人： Safdar M. Asghar , John G. Bartkowiak
IPC分类号： G06F1516
CPC分类号： G11B7/08529 , G06F9/3879 , G06F15/7842 , G11B5/012 , G11B5/5534 , G11B5/59605 , G11B5/59688 , G11B11/10563 , G11B11/10595 , G11B19/247
摘要： The communications processor of the present invention comprises, in a single integrated circuit chip, the combination of a central processing unit (CPU) having an execution unit with an arithmetic logic unit and accumulators, a program counter, memory, a clock generator, a timer, a bus interface, chip select outputs, and an interrupt processor; a digital signal processor (DSP) having an instruction set to carry out a digital signal processing algorithm, an execution unit for carrying out multiply and accumulate operations and an external interface; an address bus connected between the CPU and the DSP; a data bus connected between the CPU and the DSP; and a static scheduler for statically scheduling execution of the signal processing algorithm between the digital signal processor and the CPU.
摘要翻译：本发明的通信处理器在单个集成电路芯片中包括具有执行单元与算术逻辑单元的中央处理单元（CPU）和累加器的组合，程序计数器，存储器，时钟发生器，定时器，总线接口，片选输出和中断处理器; 具有执行数字信号处理算法的指令集的数字信号处理器（DSP），用于执行乘法和累加操作的执行单元和外部接口; 连接在CPU和DSP之间的地址总线; 连接在CPU和DSP之间的数据总线; 以及用于静态调度数字信号处理器和CPU之间的信号处理算法执行的静态调度器。

5. 发明授权

US5507037A Apparatus and method for discriminating signal noise from saturated signals and from high amplitude signals 失效
标题翻译：用于从饱和信号和高幅度信号中识别信号噪声的装置和方法
公开(公告)号：US5507037A
公开(公告)日：1996-04-09
申请号：US152316
申请日：1993-11-03
申请人： John G. Bartkowiak , Safdar M. Asghar
发明人： John G. Bartkowiak , Safdar M. Asghar
IPC分类号： H03G3/34 , H04B1/10 , H04B1/12 , H04L27/14
CPC分类号： H03G3/344 , H04B1/1027 , H04B1/123
摘要： An apparatus and method are provided for discriminating noise in a received signal. The apparatus comprises a first signal processing means, a second signal processing means, a threshold generating means for generating a threshold value. The first signal processing means generates iteration signal samples and predicted iteration signal samples, compares the iteration signal samples and predicted signal samples to generate a predicted error parameter. The second signal processing means generates a threshold adjustment value based on generated successive iteration signal samples. A logic means logically treats the prediction error parameter, the threshold adjustment value and the threshold value to generate a noise indication value.
摘要翻译：提供了一种用于识别接收信号中的噪声的装置和方法。该装置包括第一信号处理装置，第二信号处理装置，用于产生阈值的阈值产生装置。第一信号处理装置产生迭代信号样本和预测的迭代信号样本，比较迭代信号样本和预测信号样本以产生预测误差参数。第二信号处理装置基于生成的连续迭代信号样本产生阈值调整值。逻辑手段逻辑地处理预测误差参数，阈值调整值和阈值以产生噪声指示值。

6. 发明授权

US5369791A Apparatus and method for discriminating and suppressing noise within an incoming signal 失效
标题翻译：用于识别和抑制进入信号内的噪声的装置和方法
公开(公告)号：US5369791A
公开(公告)日：1994-11-29
申请号：US887076
申请日：1992-05-22
申请人： Safdar M. Asghar , John G. Bartkowiak
发明人： Safdar M. Asghar , John G. Bartkowiak
IPC分类号： H03G3/34 , H04B1/10 , H04B1/12 , H04L27/14
CPC分类号： H03G3/344 , H04B1/1027 , H04B1/123
摘要： An apparatus and method for discriminating and suppressing noise within an incoming signal which provide a first signal processing unit for processing the incoming signal to generate a first iteration signal representing average difference signal level of the incoming signal; a second signal processing unit for processing the first iteration signal to generate a second iteration signal representing specified aspects of the first iteration signal; a prediction unit for generating a predicted value for the second iteration signal from earlier samples of the second iteration signal; a logic unit for determining a threshold difference between the second iteration signal and the predicted value, the logic unit generating a logic output having a first value when the threshold difference exceeds a predetermined threshold value and having a second value when the threshold difference does not exceed the predetermined threshold value; and a muting unit for muting signals which is operatively connected to receive the incoming signal and the logic output, the muting unit responds to the logic output to mute the incoming signal when the logic output is at one value and to not mute the incoming signal when the logic output is at the other value.
摘要翻译：一种用于识别和抑制输入信号内的噪声的装置和方法，其提供用于处理输入信号的第一信号处理单元，以产生表示输入信号的平均差信号电平的第一迭代信号; 第二信号处理单元，用于处理第一迭代信号以产生表示第一迭代信号的特定方面的第二迭代信号; 预测单元，用于从所述第二迭代信号的较早样本生成所述第二迭代信号的预测值; 用于确定第二迭代信号和预测值之间的阈值差的逻辑单元，所述逻辑单元在阈值差超过预定阈值时生成具有第一值的逻辑输出，并且当阈值差不超过阈值差时具有第二值预定阈值; 以及用于静噪信号的静噪单元，其可操作地连接以接收输入信号和逻辑输出，当逻辑输出处于一个值时，静噪单元响应于逻辑输出以静音输入信号，并且当不输入信号时，逻辑输出为另一个值。

7. 发明授权

US5299233A Apparatus and method for attenuating a received signal in response to presence of noise 失效
标题翻译：响应于噪声的存在而衰减接收信号的装置和方法
公开(公告)号：US5299233A
公开(公告)日：1994-03-29
申请号：US887469
申请日：1992-05-22
申请人： Safdar M. Asghar , John G. Bartkowiak
发明人： Safdar M. Asghar , John G. Bartkowiak
IPC分类号： H03G3/34 , H04B1/10 , H04L27/14 , H03D1/06
CPC分类号： H04B1/1027 , H03G3/344
摘要： A method and apparatus provide a noise detector generating a logic output indicating presence of noise in an incoming signal and an attenuation controller for providing a stepped-response to noise operatively connected to respond to the logic output to record a count of noise detections. The attenuation controller includes an attenuation interval tracking unit for tracking the elapse of clocking intervals defining a predetermined attenuation interval; the attenuation interval tracking unit receives the noise detection signals and generates a decremental count signal for each clocking interval after the attenuation interval has elapsed, the decremental count signal is conveyed to a noise detection counter which alters the count of noise detections indicated by the logic output in response to the decremental count signal, the attenuation interval tracking unit restores the attenuation interval in response to receiving a noise detection; an attenuation signal generator is responsive to the noise detection count signal to set an attenuation factor according to a predetermined relationship between the count of noise detections and the attenuation factor, the attenuation signal being representative of the attenuation factor; and a logic unit for applying the attenuation signal to the incoming signal to attenuate the incoming signal in stepped fashion according to the attenuation factor.
摘要翻译：一种方法和装置提供了一种噪声检测器，其产生指示输入信号中存在噪声的逻辑输出，以及衰减控制器，用于向可操作地连接的噪声提供阶跃响应以响应逻辑输出以记录噪声检测的数量。衰减控制器包括衰减区间跟踪单元，用于跟踪定义预定衰减间隔的时钟间隔的经过; 衰减间隔跟踪单元接收噪声检测信号，并且在经过衰减间隔之后的每个时钟间隔产生递减计数信号，递减计数信号被传送到噪声检测计数器，该计数器改变由逻辑输出指示的噪声检测的计数响应于递减计数信号，衰减间隔跟踪单元响应于接收到噪声检测而恢复衰减间隔; 衰减信号发生器响应于噪声检测计数信号，根据噪声检测计数与衰减因子之间的预定关系来设置衰减因子，衰减信号代表衰减因子; 以及用于将衰减信号应用于输入信号以根据衰减因子以阶梯式衰减输入信号的逻辑单元。

8. 发明授权

US5459750A Apparatus and method for discriminating and suppressing noise within an incoming signal 失效
标题翻译：用于识别和抑制进入信号内的噪声的装置和方法
公开(公告)号：US5459750A
公开(公告)日：1995-10-17
申请号：US280297
申请日：1994-07-26
申请人： Dimitris Hiotakakos , Mark A. Ireton , Costas S. Xydeas , John G. Bartkowiak , Safdar M. Asghar
发明人： Dimitris Hiotakakos , Mark A. Ireton , Costas S. Xydeas , John G. Bartkowiak , Safdar M. Asghar
IPC分类号： H03G3/34 , H04B1/10 , H04L27/14
CPC分类号： H04B1/1027 , H03G3/344
摘要： An apparatus and method for discriminating and suppressing noise within an incoming signal including a first signal processor to generate a first signal representing the incoming signal; a second signal processor to generate a second signal representing the first signal; a prediction device which generates a prediction for the second signal; a logic device which determines the difference between the second signal and the prediction and generates a logic output having a first value when the difference exceeds a threshold and a second value when the difference does not exceed the threshold; and a muting device to mute the incoming signal when the logic output has one value and not mute the incoming signal when the logic output has the other value. The method includes the steps of (1) generating a first signal representing the average signal energy of the incoming signal; (2) generating a second signal representing the first signal normalized with respect to a maximum signal energy expected; (3) generating a prediction for the second signal; (4) determining a difference between the second signal and the prediction; (5) generating a control signal having a first value when the difference exceeds a threshold and a second value when the difference does not exceed the threshold; and (6) providing a muting device which responds to the control signal to mute the incoming signal when the control signal has one value and not mute the incoming signal when the control signal has the other value.
摘要翻译：一种用于识别和抑制包括第一信号处理器的输入信号内的噪声以产生表示输入信号的第一信号的装置和方法; 第二信号处理器，用于产生表示第一信号的第二信号; 产生第二信号的预测的预测装置; 确定所述第二信号和所述预测之间的差异的逻辑装置，并且当所述差异超过阈值时产生具有所述差值超过阈值的第一值的逻辑输出，以及当所述差值不超过所述阈值时产生第二值; 以及当逻辑输出具有一个值时静音输入信号的静音装置，而当逻辑输出具有另一个值时，不会使输入信号静音。该方法包括以下步骤：（1）产生表示输入信号的平均信号能量的第一信号; （2）产生表示相对于预期的最大信号能量归一化的第一信号的第二信号; （3）产生第二信号的预测; （4）确定第二信号与预测之间的差; （5）当差值超过阈值时产生具有第一值的控制信号，当差值不超过阈值时产生第二值; 以及（6）当控制信号具有一个值时，提供一个响应于控制信号使静音输入信号的静音装置，并且当控制信号具有另一个值时不提供静音。

9. 发明授权

US5043932A Apparatus having modular interpolation architecture 失效
标题翻译：具有模块插值架构的装置
公开(公告)号：US5043932A
公开(公告)日：1991-08-27
申请号：US429207
申请日：1989-10-30
申请人： Safdar M. Asghar , John G. Bartkowiak
发明人： Safdar M. Asghar , John G. Bartkowiak
IPC分类号： H03M1/66 , G06F17/17 , G06J1/00 , H04B14/04
CPC分类号： G06F17/17 , G06J1/00
摘要： An apparatus adaptable for use with a digital-analog conversion device for effecting communications from a digital device to an analog device, having a digital-analog circuit for converting interpolated outgoing digital signals to outgoing analog signals. The apparatus further has a digital signal processing circuit for interpolating outgoing digital signals received from the digital device and providing an interpolated outgoing digital signal to the digital-analog device. The digital signal processing circuit is comprised of a plurality of modules which are configured so that a specified set of the plurality of modules effects a specified number of iterations of interpolation. The modules are further designed so that additional modules may be added to the specified set of modules to increase the iterations of interpolation.

10. 发明授权

US4999626A Apparatus having a modular decimation architecture 失效
标题翻译：具有模块化抽取架构的装置
公开(公告)号：US4999626A
公开(公告)日：1991-03-12
申请号：US428628
申请日：1989-10-30
申请人： Safdar M. Asghar , John G. Bartkowiak
发明人： Safdar M. Asghar , John G. Bartkowiak
IPC分类号： H03M1/12 , G06F3/05 , H03H17/06 , H04B14/04
CPC分类号： H03H17/0664 , G06F3/05
摘要： An apparatus adaptable for use with an analog-digital conversion device for effecting communications between an analog device and a digital device, the analog-digital conversion device converting incoming analog signals received from the analog device to incoming digital signals. The apparatus has a digital signal processing circuit for decimating the incoming digital signals and providing a decimated incoming digital signal to the digital device.The digital signal processing circuit is comprised of a plurality of modules which are configured so that a specified set of the plurality of modules effects a specified number of iterations of decimation. The modules are further designed so that additional modules may be added to the specified set of modules to increase the iterations of decimation.

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