会员体验
专利管家（专利管理）
工作空间（专利管理）
风险监控（情报监控）
数据分析（专利分析）
侵权分析（诉讼无效）
联系我们
交流群
官方交流：
QQ群： 891211   
微信请扫码    >>>
现在联系顾问~
下载
著录项
PDF全文
热词
    • 4. 发明授权
      US4588980A Residue to analog converter 失效
    • Residue to analog converter
    • 残留模拟转换器
    • US4588980A
    • 1986-05-13
    • US653423
    • 1984-09-24
    • Peter S. Bernardson
    • Peter S. Bernardson
    • H03M7/18 , H03M1/12
    • H03M7/18
    • A residue to analog converter associated with residue numbers {m1,m2,m3} of the residue number system defined by the moduli set {p1=2.sup.n -1, p2=2.sup.n, p3=2.sup.n +1} and which does not require memory comprises five standard binary adder circuits, apparatus for performing multiplication by bit shifting, and a modulo p1 p3 adder circuit. First and second binary adders combine the residue signals m1 and m3 to produce sum and difference signals which are bit shifted by grounding 2n-1 and n-1 lines, respectively, and locating them as less significant bit lines ahead of these sum and difference signal lines. A modulo p1*p3 adder sums these bit shifted signals. A third binary adder, which ignores overflow, performs a modulo p2=2.sup.n subtraction of m2 from the n less significant bits of the modulo p1*p3 sum signal to produce a second difference signal. This second difference signal is bit shifted by 2n grounded lines that are connected as less significant bit lines ahead of this signal, and then subtracted from this bit shifted signal in a fourth binary adder to produce a correction signal. The modulo p1*p3 sum signal and the correction signal are summed in a fifth binary adder to produce a three dimensional binary signal r(m1,m2,m3) that is representative of a residue signal {m1,m2,m3}. The corresponding analog signal is produced with a standard D/A converter. Structure for implementing the modulo p1*p3 adder circuit with adders that are all standard binary adders is disclosed.
    • 与由模数组{p1 = 2n-1，p2 = 2n，p3 = 2n + 1}定义并且不需要存储器的残差数系统的残余数{m1，m2，m3}相关联的残差模拟转换器包括 五个标准二进制加法器电路，用于通过比特移位执行乘法的装置和模p1 p3加法器电路。 第一和第二二进制加法器组合残差信号m1和m3，以产生通过分别接地2n-1和n-1线位移的和和差分信号，并将它们定位在这些和和差信号之前的较低有效位线 线条。 模p1 * p3加法器将这些位移信号相加。 忽略溢出的第三个二进制加法器对模p1 * p3和信号的n个较低有效位进行m2 p2 = 2n的减法，以产生第二差分信号。 该第二差分信号被移位了2n个接地线，其被连接作为该信号之前的较低有效位线，然后在第四个二进制加法器中从该位移信号中减去以产生校正信号。 模p1 * p3和信号和校正信号在第五个二进制加法器中求和，以产生代表残留信号{m1，m2，m3}的三维二进制信号r（m1，m2，m3）。 相应的模拟信号由标准D / A转换器产生。 公开了用于实现具有所有标准二进制加法器的加法器的模p1 * p3加法器电路的结构。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US4584561A Method of residue to analog conversion 失效
    • Method of residue to analog conversion
    • 残留模拟转化方法
    • US4584561A
    • 1986-04-22
    • US653402
    • 1984-09-24
    • Peter S. Bernardson
    • Peter S. Bernardson
    • H03M7/18 , H03M1/12
    • H03M7/18
    • In a residue number system defined by the moduli set {p1=2.sup.n -1, p2=2.sup.n, p3=2.sup.n +1}, a method of converting residue numbers {m1,m2,m3} to associated analog signals r(m1,m2,m3) comprises the steps of selecting a first binary signal satisfying the relationships .vertline.m1*S3+m3*S1.vertline..sub.p1*p3 (where the constant S1=p1*p2/2 and S3=p2*p3/2) from a first look-up table; and summing the n less significant bits of this first digital signal and the negative of the residue digit signal m2 in a first binary adder for generating a second binary signal that is representative of the difference therebetween, taken modulo p2. This second binary signal addresses a second look-up table containing third binary signals which correspond to possible values of the product of the second binary signal and p1 and p3. Selected first and third binary signals are summed in a second binary adder for producing a binary output signal r(m1,m2,m3) that is representative of the residue number {m1,m2,m3}. This binary output signal is converted to a corresponding analog signal in a standard D/A converter. In an alternate method, 2n binary 0's are stuffed as less significant bits of the second binary signal prior to subtracting the latter from this bit shifted signal for producing the third binary signal. In yet another method, the first binary signal is obtained by selecting the binary signals m1*S3 and m3*S1 from associated look-up tables prior to summing them modulo p1*p3.
    • 在由模数组{p1 = 2n-1，p2 = 2n，p3 = 2n + 1}定义的残差数系统中，将残差数{m1，m2，m3}转换为相关模拟信号r（m1，m2） ，m3）包括以下步骤：从第一个数据库中选择满足关系| m1 * S3 + m3 * S1|p1 * p3（其中常数S1 = p1 * p2 / 2和S3 = p2 * p3 / 2）的第一二进制信号 查找表; 并在第一个二进制加法器中对该第一数字信号的n个较低有效位和残差数字信号m2的负相加，以产生代表它们之间的差的第二二进制信号，采用模p2。 该第二二进制信号寻址包含与第二二进制信号和p1和p3的乘积的可能值对应的第三二进制信号的第二查询表。 选择的第一和第三二进制信号在第二个二进制加法器中求和，以产生代表残差数{m1，m2，m3}的二进制输出信号r（m1，m2，m3）。 该二进制输出信号在标准D / A转换器中转换成相应的模拟信号。 在另一种方法中，将2n二进制0作为第二二进制信号的较低有效位填充，然后从该位移信号中减去后者，产生第三二进制信号。 在另一种方法中，通过从相关联的查找表中选择二进制信号m1 * S3和m3 * S1获得第一个二进制信号，然后对它们进行模p1 * p3求和。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US4816805A Residue number system shift accumulator decoder 失效
    • Residue number system shift accumulator decoder
    • 残差系统移位累加器解码器
    • US4816805A
    • 1989-03-28
    • US009725
    • 1987-02-02
    • William M. Vojir , Joel R. Davidson
    • William M. Vojir , Joel R. Davidson
    • H03H17/02 , H03M7/18 , H03M7/00
    • H03H17/0242 , H03M7/18
    • Signal processing techniques are disclosed for applications such as finite impulse response filtering. After initial processing in residue number system (RNS) channels, the signals are converted from residue form to a true external representation of the filter output. The conversion employs a chinese remainder theorem decoder and shift accumulator controlled to utilize adaptive modulo reduction. As a consequence, each modulus function value is reduced during computation when it exceeds the modulus and not at the end of the function evaluation. This reduces hardware requirements by minimizing the arithmetic word length. In implementing the technique, each function value is tested to see if it is within a modulus range and the corresponding modulus value is subtracted if it is not. This is done as many times as is necessary to bring each function value within the range. By utilizing this technique, speed and computational accuracy are improved in filter processes thereby producing improved performance in radar, seismic, acoustic and other applications which depend on such filter characteristics.
    • 公开了用于诸如有限脉冲响应滤波的应用的信号处理技术。 在残留号码系统（RNS）通道进行初始处理后，信号从残留格式转换为滤波器输出的真实外部表示。 转换采用中文余数定理解码器和控制的移位累加器来利用自适应模减。 因此，当其超过模量并且不在功能评估结束时，每个模数函数值在计算期间减小。 这通过最小化算术字长度来降低硬件要求。 在实施该技术时，测试每个功能值，以查看其是否在模数范围内，如果不是则减去相应的模数值。 这是为了使每个功能值在该范围内所必需的次数。 通过利用这种技术，滤波器过程的速度和计算精度得到改善，从而在雷达，地震，声学和其他应用中取决于这种滤波器特性的改进性能。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US4584563A Method of residue to analog conversion 失效
    • Method of residue to analog conversion
    • 残留模拟转化方法
    • US4584563A
    • 1986-04-22
    • US653412
    • 1984-09-24
    • Peter S. Bernardson
    • Peter S. Bernardson
    • H03M7/18 , H03M1/12
    • H03M7/18
    • In a residue number system defined by the moduli set {p1=2.sup.n -1, p2=2.sup.n, p3=2.sup.n +1}, a method of converting residue number signals {m1,m2,m3} to associated analog signals r(m1,m2,m3), and that does not require memory devices, comprises the steps of generating a pair of binary signals that are the sum and difference of the residue numbers m1 and m3, bit shifting these sum and difference signals by inserting 2n-1 and n-1 binary 0's as less significant bits thereof, and summing these bit shifted signals modulo p1*p3 to produce a two dimensional binary signal r(m1,m3). A correction signal is generated by modulo p2=2.sup.n summing the n less significant bits of the signal r(m1,m3 ) and the negative of the residue signal m2 to produce a second difference signal, bit shifting this second difference signal by inserting 2n binary 0's as less significant bits thereof and subtracting the second difference signal from this bit shifted signal to produce the correction signal. The signal r(m1,m3) and the correction signal are summed for producing a binary representation r(m1,m2,m3) of a given residue number {m1,m2,m3} . This binary signal is converted to the corresponding analog signal in a standard D/A converter. In a preferred embodiment, apparatus for performing the modulo p1*p3 summation is implemented with combining circuits that may be all standard binary adders so that all of the combining is done with standard binary adders and that no memory devices are required to perform the desired residue to binary conversion.
    • 在由模数组{p1 = 2n-1，p2 = 2n，p3 = 2n + 1}定义的残差数系统中，将残差数信号{m1，m2，m3}转换为相关联的模拟信号r（m1， m2，m3），并且不需要存储器件，包括以下步骤：产生作为残差号m1和m3的和和差的二进制信号，通过插入2n-1和 将n-1个二进制0作为较低有效位，并将这些位移信号相加p1 * p3，以产生二维二进制信号r（m1，m3）。 通过模p2 = 2n对信号r（m1，m3）的n个较低有效位和残留信号m2的负值进行求和来产生校正信号以产生第二差分信号，通过插入2n个二进制位来移位该第二差分信号 0作为较低有效位，并从该位移信号中减去第二差分信号以产生校正信号。 信号r（m1，m3）和校正信号相加以产生给定残留数{m1，m2，m3}的二进制表示r（m1，m2，m3）。 该二进制信号在标准D / A转换器中转换为相应的模拟信号。 在优选实施例中，用于执行模p1 * p3求和的装置由组合电路实现，该组合电路可以是所有标准的二进制加法器，以便所有组合都用标准二进制加法器完成，并且不需要存储器件来执行所需的残留 到二进制转换。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
每页展示10个专利
每页展示10个专利
每页展示20个专利
每页展示50个专利
每页展示100个专利

IPRDB

最新中国发明专利 最新美国发明专利 技术领域 专利库 专利分类库 国际专利分类库

热门服务

会员版试用 API 数据接口 找代理 知嘟嘟专利交易 排行榜 大学排行榜 专利百科

关于我们

平台介绍 战略合作 网站地图

友情链接

知嘟嘟专利交易 国家知识产权局 中国商标网

联系方式


©2019-2023 上海吉码数字技术有限公司 版权所有，并保留所有权利 沪ICP备20016256号-6 沪公网安备31011702005475号