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1. 发明申请

US20180136681A1 VOLTAGE REFERENCE BUFFER CIRCUIT 审中-公开
公开(公告)号：US20180136681A1
公开(公告)日：2018-05-17
申请号：US15800935
申请日：2017-11-01
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： CHE-WEI CHANG , KAI-YIN LIU , LIANG-HUAN LEI , SHIH-HSIUNG HUANG
IPC分类号： G05F1/618 , G05F3/24 , G05F1/40 , G05F1/571 , G05F1/573 , G05F1/575
CPC分类号： G05F1/618 , G05F1/40 , G05F1/571 , G05F1/573 , G05F1/575 , G05F3/247
摘要： The present invention discloses a voltage reference buffer circuit. An embodiment of the voltage reference buffer circuit includes: a first bias generator configured to generate a first bias voltage; a second bias generator configured to generate a second bias voltage different from the first bias voltage; a first driving component coupled to a high voltage terminal, the first bias generator and a reference voltage output terminal, and configured to control a reference voltage at the reference voltage output terminal according to the first bias voltage; and a second driving component coupled to the reference voltage output terminal, the second bias generator and a low voltage terminal, and configured to control a current between the reference voltage output terminal and the second driving component according to the second bias voltage.

2. 发明申请

US20220158649A1 Control circuit of pipeline ADC 有权
公开(公告)号：US20220158649A1
公开(公告)日：2022-05-19
申请号：US17410382
申请日：2021-08-24
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： PAN ZHANG , KAI-YIN LIU , SHIH-HSIUNG HUANG , WEI-JYUN WANG
IPC分类号： H03M1/16 , H03M1/46 , H03M1/44 , H03M1/80 , H03M1/12 , H03M1/10
摘要： A control circuit of a pipeline analog-to-digital converter (ADC) is provided. The pipeline ADC includes a multiplying digital-to-analog converter (MDAC) which includes a capacitor. The control circuit includes six switches and two buffer circuits. The first and second switches are respectively coupled between one end of the capacitor and the first and second reference voltages. The output terminals of the first and second buffer circuits are respectively coupled to the first and second switches. The input terminal of the first buffer circuit is coupled to the third reference voltage through the third switch, or receives a control signal through the fifth switch. The input terminal of the second buffer circuit is coupled to the fourth reference voltage through the fourth switch, or receives the control signal through the sixth switch. The first and second reference voltages are different, and the first and second switches are not turned on simultaneously.

3. 发明申请

US20210382512A1 Voltage reference buffer circuit 有权
公开(公告)号：US20210382512A1
公开(公告)日：2021-12-09
申请号：US17405380
申请日：2021-08-18
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： CHE-WEI CHANG , KAI-YIN LIU , LIANG-HUAN LEI , SHIH-HSIUNG HUANG
IPC分类号： G05F1/618 , G05F3/24 , G05F1/575 , G05F1/571 , G05F1/573 , G05F1/40
摘要： Disclosed is a voltage reference buffer circuit including a first, second, third, and fourth bias generators and a first, second, third, and fourth driving components. The first, second, third, and fourth bias generators generate bias voltages to control the first, second, third, and fourth driving components respectively. The first, second, third, and fourth driving components are coupled in sequence, wherein the first and second driving components are different types of transistors and jointly output a first reference voltage, the third and fourth driving components are different types of transistors and jointly output a second reference voltage, and the group of the first and second driving components is separated from the group of the third and fourth driving components by a resistance load.

4. 发明公开

US20230179156A1 Signal receiving apparatus and programmable gain amplifier having mode-switching mechanism 审中-公开
公开(公告)号：US20230179156A1
公开(公告)日：2023-06-08
申请号：US17865810
申请日：2022-07-15
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： YUN-TSE CHEN , KAI-YIN LIU
IPC分类号： H03F3/45 , H03H19/00 , H03H7/12
CPC分类号： H03F3/45076 , H03H19/004 , H03H7/12
摘要： The present invention discloses a programmable gain amplifier having mode-switching mechanism. An operational amplifier includes a first input terminal, a second input terminal and an output terminal. The second input terminal is coupled to a ground terminal. The output terminal generates an output signal. A variable resistor and a first switch are coupled in series between a first terminal and a second terminal that coupled to the first input terminal. A first variable capacitor and a second switch are coupled in series between the first terminal and the second terminal. A second variable capacitor and a third switch are coupled in series between the first terminal and the ground terminal. A low-pass resistor and a low-pass capacitor are coupled in parallel between the first input terminal and the output terminal. An input resistor is coupled between a signal input terminal and the first terminal to receive an input signal from the signal input terminal. The first, the second and the third switches receive a set of mode-switching signals to switch to form a path or an open-circuit.

5. 发明申请

US20160004273A1 Clock generator, communication device and sequential clock gating circuit 有权
标题翻译：时钟发生器，通信设备和顺序时钟门控电路
公开(公告)号：US20160004273A1
公开(公告)日：2016-01-07
申请号：US14720056
申请日：2015-05-22
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： CHIH-JUNG CHIANG , SHUN-TE TSENG , KAI-YIN LIU , JIAN-RU LIN
IPC分类号： G06F1/10 , G06F1/08
CPC分类号： G06F1/10 , G06F1/06 , G06F1/08 , H03K19/0016
摘要： The present invention discloses a clock generator comprising: an oscillator operable to generate a reference clock; a multi-phase clock generating circuit operable to generate a plurality of output clocks of the same frequency but different phases according to the reference clock and stop or start outputting the output clocks according to a power control signal; a sequential clock gating circuit operable to sequentially stop or start outputting a plurality of gated clocks according to a gate control signal and maintain an output cycle number relation between the gated clocks even though the multi-phase clock generating circuit stops and then starts outputting the output clocks; and a clock operation control circuit operable to provide the power control signal and the gate control signal.
摘要翻译：本发明公开了一种时钟发生器，包括：可操作以产生参考时钟的振荡器; 多相时钟发生电路，用于根据参考时钟产生相同频率但不同相位的多个输出时钟，并根据功率控制信号停止或开始输出输出时钟; 顺序时钟门控电路，其可操作以根据门控制信号顺序地停止或开始输出多个选通时钟，并且即使多相时钟产生电路停止，并且仍然保持门控时钟之间的输出周期数关系，并且然后开始输出输出时钟以及时钟操作控制电路，其可操作以提供功率控制信号和门控制信号。

6. 发明申请

US20220069831A1 FLASH ANALOG TO DIGITAL CONVERTER AND CALIBRATION METHOD 有权
公开(公告)号：US20220069831A1
公开(公告)日：2022-03-03
申请号：US17333063
申请日：2021-05-28
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： SHIH-HSIUNG HUANG , YING-CHENG WU , CHIEN-MING WU , KAI-YIN LIU
IPC分类号： H03M1/10
摘要： A flash analog to digital converter includes double differential comparator circuits and a calibration circuit. Each double differential comparator circuit compares a first input signal with a corresponding voltage in a first set of reference voltages, and compares a second input signal with a corresponding voltage in a second set of reference voltages, in order to generate a corresponding signal in first signals. The calibration circuit outputs a first test signal to be the first input signal and outputs a second test signal to be the second input signal in a test mode, and calibrates a common mode level of each of the first input signal and the second input signal, or calibrates at least one first reference voltage in the first set of reference voltages and at least one second reference voltage in the second set of reference voltages according to a distribution of the first signals.

7. 发明申请

US20180143225A1 Detection Circuit for Power over Ethernet and Detection Current Generation Method Thereof 审中-公开
公开(公告)号：US20180143225A1
公开(公告)日：2018-05-24
申请号：US15714946
申请日：2017-09-25
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： KAI-YIN LIU , HUI-MIN HUANG
IPC分类号： G01R19/00 , G05B11/01 , H04L12/10
CPC分类号： G01R19/0092 , G05B11/01 , G06F1/00 , H04L12/10 , Y02D50/30
摘要： A detection circuit for power over Ethernet (PoE) and a detection current generation method thereof. The detection circuit for PoE is installed in power sourcing equipment (PSE), and generates a first detection current in a first detection mode to detect a power device (PD) of a first type and generates a second detection current in a second detection mode to detect a PD of a second type. The detection circuit of PoE includes a first current source group that has at least one first current source for generating part of the first detection current in the first detection mode, and a second current source group that has multiple second current sources for generating part of the first detection current in the first detection mode and generating the second detection current in the second detection mode. The first current source group does not generate current in the second detection mode.

8. 发明公开

US20230421165A1 Successive approximation analog to digital conversion circuit and method having optimized linearity 审中-公开
公开(公告)号：US20230421165A1
公开(公告)日：2023-12-28
申请号：US18211852
申请日：2023-06-20
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： WEI-JYUN WANG , KAI-YIN LIU , SHIH-HSIUNG HUANG , CHIEN-MING WU
IPC分类号： H03M1/06
CPC分类号： H03M1/0604
摘要： The present invention discloses a SAADC circuit having optimized linearity. A lower-bit capacitor array includes lower-bit capacitors. A higher-bit capacitor array includes unit capacitors. In an initializing mode, a control circuit sorts the unit capacitors according to unit capacitances thereof such that the unit capacitors are configured to be higher-bit capacitors having a linearity parameter within a predetermined range. In an operation mode, the capacitor array receives an analog input signal and a reference voltage to generate an analog output signal, a comparator generates a comparison result according to the analog output signal and the control circuit generates an enabling signal according to the comparison result based on the successive approximation mechanism to selectively enable the higher-bit and the lower-bit capacitors to connect to the reference voltage by using the capacitor enabling circuit and outputs a digital output signal according to the final comparison result.

9. 发明申请

US20220140836A1 PIPELINE ANALOG TO DIGITAL CONVERTER AND TIMING ADJUSTMENT METHOD 有权
公开(公告)号：US20220140836A1
公开(公告)日：2022-05-05
申请号：US17400152
申请日：2021-08-12
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： SHIH-HSIUNG HUANG , PAN ZHANG , KAI-YIN LIU , CHIEN-MING WU
IPC分类号： H03M1/06 , H03M1/16 , H03M1/10 , H03M1/66
摘要： A pipeline analog to digital converter (ADC) includes converter circuitries, a detector circuitry, and a clock generator circuit. The converter circuitries sequentially convert an input signal to be digital codes. One of the converter circuitries includes a sub-ADC circuit and a multiplying digital to analog converter (MDAC) circuit. The sub-ADC circuit performs a quantization according to a first signal to generate a corresponding one of the digital codes, in which the first signal is the input signal or a previous stage residue signal. The MDAC circuit processes the corresponding one of the digital codes in response to a first clock signal, in order to generate a current stage residue signal. The detector circuitry detects whether the quantization is complete, in order to generate a control signal. The clock generator circuit adjusts a timing of the first clock signal according to the control signal.

10. 发明申请

US20180138895A1 RESISTANCE CALIBRATION CIRCUIT AND DEVICE 审中-公开
公开(公告)号：US20180138895A1
公开(公告)日：2018-05-17
申请号：US15694550
申请日：2017-09-01
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： KAI-YIN LIU , HUI-MIN HUANG
IPC分类号： H03H11/30 , G05F3/26
CPC分类号： H03H11/30 , G05F3/262
摘要： The present invention discloses a resistance calibration circuit. An embodiment of the resistance calibration circuit includes: a reference voltage outputting circuit operable to output a reference voltage; an adjustable internal resistor including at least one positive temperature coefficient resistor and at least one negative temperature coefficient resistor; a reference current generating circuit operable to generate an internal resistor reference current according to the reference voltage and the internal resistor and generate an external resistor reference current according to the reference voltage and an external resistor; and a comparison and control circuit operable generate a comparison result according to the internal and external resistor reference currents, and adjust the internal resistor according to the comparison result till the comparison result indicates that the difference between the internal and external resistor reference currents is less than a predetermined threshold or unable to be further reduced.

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