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1. 发明授权

US09170596B2 Integrated circuits having cascode transistor 有权
标题翻译：具有共源共栅晶体管的集成电路
公开(公告)号：US09170596B2
公开(公告)日：2015-10-27
申请号：US14301409
申请日：2014-06-11
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Yvonne Lin
IPC分类号： G05F1/10 , H03K3/01 , G05F3/24 , H01L25/03
CPC分类号： G05F3/247 , G05F3/30 , H01L25/03 , H01L2924/0002 , H03F1/223 , H01L2924/00
摘要： An integrated circuit includes a first circuit. The first circuit includes a first transistor having a first dopant type. The first circuit further includes a first cascode transistor having the first dopant type, wherein the first cascode transistor connected in series with the first transistor. The first circuit further includes a second transistor having a second dopant type opposite to the first dopant type, wherein the second transistor is connected in series with the first transistor. The first circuit includes a second cascode transistor having the second dopant type, wherein the second cascode transistor is connected in series with the second transistor. The integrated circuit further includes a first bias circuit configured to adjust a threshold voltage of at least one of the first cascode transistor or the second cascode transistor.
摘要翻译：集成电路包括第一电路。第一电路包括具有第一掺杂剂类型的第一晶体管。第一电路还包括具有第一掺杂剂类型的第一共源共栅晶体管，其中与第一晶体管串联连接的第一共源共栅晶体管。第一电路还包括具有与第一掺杂剂类型相反的第二掺杂剂类型的第二晶体管，其中第二晶体管与第一晶体管串联连接。第一电路包括具有第二掺杂剂类型的第二共源共栅晶体管，其中第二共源共栅晶体管与第二晶体管串联连接。集成电路还包括被配置为调节第一共源共栅晶体管或第二共源共栅晶体管中的至少一个的阈值电压的第一偏置电路。

2. 发明授权

US09054577B2 Charge pump and method of biasing deep N-well in charge pump 有权
标题翻译：电荷泵和偏置电荷泵深N阱的方法
公开(公告)号：US09054577B2
公开(公告)日：2015-06-09
申请号：US14212345
申请日：2014-03-14
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Yvonne Lin , Tien-Chun Yang
IPC分类号： H02M3/07 , G11C5/14
CPC分类号： H02M3/07 , G11C5/145 , H02M3/073 , H02M2003/075
摘要： A charge pump has at least one charge pump stage. Each charge pump stage includes at least one NMOS device. The at least one NMOS device has a deep N-well (DNW), a gate and a drain, and is coupled to at least one capacitor, a first node, a second node and a switch. For the at least one NMOS device, the gate is capable of receiving a different signal from the drain. The first node is arranged to receive an input signal. The switch is coupled between the at least one NMOS device and a ground. A drain of the switch is coupled to a deep N-well of the switch. The at least one capacitor is arranged to store electrical charges. The charge pump stage is configured to supply the electrical charges to the second node. The DNW is coupled to the ground for a negative pump operation.
摘要翻译：电荷泵具有至少一个电荷泵级。每个电荷泵级包括至少一个NMOS器件。至少一个NMOS器件具有深N阱（DNW），栅极和漏极，并且耦合到至少一个电容器，第一节点，第二节点和开关。对于至少一个NMOS器件，栅极能够从漏极接收不同的信号。第一节点布置成接收输入信号。开关耦合在至少一个NMOS器件和地之间。开关的漏极耦合到开关的深N阱。至少一个电容器被布置成存储电荷。电荷泵级被配置为将电荷提供给第二节点。 DNW联接到地面进行负泵操作。

3. 发明授权

US09385118B2 Capacitor array having capacitor cell structures 有权
标题翻译：具有电容器单元结构的电容阵列
公开(公告)号：US09385118B2
公开(公告)日：2016-07-05
申请号：US14692811
申请日：2015-04-22
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Yvonne Lin , Wen-Ting Chu
IPC分类号： G11C11/34 , H01L27/08 , H01L29/94 , H01L27/115 , H01L49/02 , G11C16/08 , G11C29/00 , H01L27/06 , G11C16/04
CPC分类号： H01L27/0805 , G11C16/0408 , G11C16/08 , G11C29/82 , H01L27/0629 , H01L27/0802 , H01L27/11526 , H01L28/60 , H01L29/94
摘要： A capacitor array includes a plurality of capacitor cell structures. The capacitor cell structures of the plurality of cell structures each includes a first capacitor electrode, a second capacitor electrode over the first capacitor electrode, a third capacitor electrode adjacent to first sidewalls of the first and second capacitor electrodes, a fourth capacitor electrode adjacent to second sidewalls of the first and second capacitor electrodes, and a fifth capacitor electrode adjacent to the fourth capacitor electrode.
摘要翻译：电容器阵列包括多个电容器单元结构。多个单元结构的电容器单元结构各自包括第一电容器电极，第一电容器电极上的第二电容器电极，与第一和第二电容器电极的第一侧壁相邻的第三电容器电极，与第二电容器电极相邻的第四电容器电极第一和第二电容器电极的侧壁和与第四电容器电极相邻的第五电容器电极。

4. 发明授权

US09042171B2 Integrated circuit including a voltage divider and methods of operating the same 有权
标题翻译：集成电路包括分压器及其操作方法
公开(公告)号：US09042171B2
公开(公告)日：2015-05-26
申请号：US14315415
申请日：2014-06-26
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Yvonne Lin , Wen-Ting Chu
IPC分类号： G11C11/34 , H01L27/115 , H01L29/94 , H01L49/02 , G11C16/08 , G11C29/00 , H01L27/06 , G11C16/04 , H01L27/08
CPC分类号： H01L27/0805 , G11C16/0408 , G11C16/08 , G11C29/82 , H01L27/0629 , H01L27/0802 , H01L27/11526 , H01L28/60 , H01L29/94
摘要： An integrated circuit includes at least one memory array and at least one capacitor array over a substrate. The at least one capacitor array includes a plurality of capacitor cell structures. The capacitor cell structures of the plurality of cell structures comprise a first capacitor electrode over the substrate. A second capacitor electrode is over the first capacitor electrode. A third capacitor electrode is adjacent to first sidewalls of the first and second capacitor electrodes. A fourth capacitor electrode is adjacent to second sidewalls of the first and second capacitor electrodes. A fifth capacitor electrode is over the substrate and adjacent to the fourth capacitor electrode.
摘要翻译：集成电路包括至少一个存储器阵列和衬底上的至少一个电容器阵列。所述至少一个电容器阵列包括多个电容器单元结构。多个电池结构的电容器单元结构包括在该衬底上的第一电容器电极。第二电容器电极在第一电容器电极之上。第三电容器电极与第一和第二电容器电极的第一侧壁相邻。第四电容器电极与第一和第二电容器电极的第二侧壁相邻。第五电容器电极在衬底上并且与第四电容器电极相邻。

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