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1. 发明授权

US10312185B2 Inductively coupled microelectromechanical system resonator 有权
公开(公告)号：US10312185B2
公开(公告)日：2019-06-04
申请号：US15726284
申请日：2017-10-05
申请人： Texas Instruments Incorporated
发明人： Bichoy Bahr , Baher Haroun , Ali Kiaei
IPC分类号： H01L23/495 , B81C1/00 , G01C19/56 , H01L23/00 , B81B7/02 , B81B7/00
摘要： An integrated circuit package includes a first die that has a microelectromechanical system (MEMS) resonator coupled to a coil. A second die includes a coil fabricated on a top surface of the second die, and an electronic circuit with tank circuit terminals fabricated on the second die and coupled to the second coil. The second die is positioned adjacent the first die such that the first coil is operable to electromagnetically couple to the second coil.

2. 发明授权

US09806673B2 Class-E outphasing power amplifier with efficiency and output power enhancement circuits and method 有权
公开(公告)号：US09806673B2
公开(公告)日：2017-10-31
申请号：US15165339
申请日：2016-05-26
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Aritra Banerjee , Joonhoi Hur , Baher Haroun , Nathan Richard Schemm , Rahmi Hezar , Lei Ding
IPC分类号： H03F3/217 , H03F1/02 , H03F3/193 , H03F3/21 , H03F3/45
CPC分类号： H03F1/0205 , H03F1/0294 , H03F3/193 , H03F3/211 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/2176 , H03F3/45179 , H03F2200/391 , H03F2200/451 , H03F2203/21139 , H03F2203/21142
摘要： An outphasing amplifier includes a first class-E power amplifier (16-1) having an output coupled to a first conductor (31-1) and an input receiving a first RF drive signal (S1(t)). A first reactive element (CA-1) is coupled between the first conductor and a second conductor (30-1). A second reactive element (LA-1) is coupled between the second conductor and a third conductor (32-1). A second class-E power amplifier (17-1) includes an output coupled to a fourth conductor (31-2) and an input coupled to a second RF drive signal (S2(t)), a third reactive element (CA-3) coupled between the second and fourth conductors. Outputs of the first and second power amplifiers are combined by the first, second and third reactive elements to produce an output current in a load (R). An efficiency enhancement circuit (LEEC-1) is coupled between the first and fourth conductors to improve power efficiency at back-off power levels. Power enhancement circuits (20-1,2) are coupled to the first and fourth conductors, respectively.

3. 发明授权

US09021322B2 Probeless testing of pad buffers on wafer 有权
公开(公告)号：US09021322B2
公开(公告)日：2015-04-28
申请号：US14089069
申请日：2013-11-25
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/317 , G01R31/3185 , G11C29/00 , G11C29/02 , G11C29/48 , G11C29/32
CPC分类号： G01R31/3177 , G01R31/31715 , G01R31/318505 , G01R31/318511 , G01R31/318533 , G01R31/318558 , G01R31/318572 , G01R31/318594 , G11C29/006 , G11C29/022 , G11C29/48 , G11C2029/3202
摘要： The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.

4. 发明申请

US20140133437A1 METHOD FOR DETERMINING THE LOCATION OF CONTROL CHANNELS IN THE UPLINK OF COMMUNICATION SYSTEMS 审中-公开
标题翻译：用于确定通信系统上行链路中控制信道位置的方法
公开(公告)号：US20140133437A1
公开(公告)日：2014-05-15
申请号：US14157023
申请日：2014-01-16
申请人： TEXAS INSTRUMENT INCORPORATED
发明人： ARIS PAPASAKELLARIOU
IPC分类号： H04W72/04 , H04L5/00
CPC分类号： H04W72/0413 , H04L1/1854 , H04L5/0007 , H04L5/0053 , H04L5/0055 , H04L5/0057 , H04L5/0064 , H04L5/0091 , H04W72/042
摘要： Embodiments of the Invention provide methods for user equipments to implicitly determine the location for the transmission of uplink control signaling information, that is in response to downlink data packet transmissions, using information that is already available through the downlink control, signaling for the respective downlink scheduling assignments. No additional explicit downlink control signaling is required for the transmission of the above uplink control signaling from each user equipment.
摘要翻译：本发明的实施例提供了用于用户设备隐含地确定用于传输上行链路控制信令信息的位置的方法，所述上行链路控制信令信息是响应于下行链路数据分组传输，使用已经通过下行链路控制可用的信息，用于相应的下行链路调度的信令作业。从每个用户设备传输上述上行链路控制信令不需要额外的显式下行链路控制信令。

5. 发明申请

US20100231299A1 AUTOMATIC GAIN CONTROL 有权
标题翻译：自动增益控制
公开(公告)号：US20100231299A1
公开(公告)日：2010-09-16
申请号：US12400898
申请日：2009-03-10
申请人： Zhengyu Wang , Xiaoju Wu
发明人： Zhengyu Wang , Xiaoju Wu
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F3/45179 , H03F3/45659 , H03F2200/411 , H03F2203/45418 , H03F2203/45424 , H03F2203/45528 , H03F2203/45536 , H03F2203/45594 , H03F2203/45596 , H03F2203/45652 , H03G1/0029 , H03G1/0088
摘要： A method and system for providing automatic gain control for a differential amplifier are provided. An impedance network is set to have a first impedance that corresponds to a first gain for a differential amplifier, which amplifies an input signal by the first gain. Once the amplified input signal is greater than a first threshold voltage, the impedance network is set to have a second impedance that corresponds to a second gain for the differential amplifier, which amplifies the input signal. Once amplified input signal is greater than a second threshold voltage and a predetermined period has lapsed, the impedance network is reset to have the first impedance that corresponds to a first gain for the differential amplifier.
摘要翻译：提供了一种用于为差分放大器提供自动增益控制的方法和系统。阻抗网络被设置为具有对应于差分放大器的第一增益的第一阻抗，该差分放大器通过第一增益来放大输入信号。一旦放大的输入信号大于第一阈值电压，阻抗网络被设置为具有对应于放大输入信号的差分放大器的第二增益的第二阻抗。一旦放大输入信号大于第二阈值电压并且预定周期已经过去，则阻抗网络被复位为具有对应于差分放大器的第一增益的第一阻抗。

6. 发明申请

US20080162769A1 Systems and Methods for Improving Data Transfer between Devices 有权
标题翻译：改进设备间数据传输的系统和方法
公开(公告)号：US20080162769A1
公开(公告)日：2008-07-03
申请号：US11967086
申请日：2007-12-29
申请人： Roy D. Wojciechowski
发明人： Roy D. Wojciechowski
IPC分类号： G06F13/28
CPC分类号： G06F13/4059
摘要： Systems and methods are disclosed for detecting a first device on a first bus issuing a read request for an amount of data to a second device on a second bus. The systems and methods further include detecting a bridge requesting a first portion of the data from the second device on behalf of the first device in response to the bridge receiving the read request, where the bridge couples the first bus to the second bus. In addition, the systems and methods include triggering the bridge to request an additional portion of the data on behalf of the first device.
摘要翻译：公开了用于检测在第二总线上向第二设备发出数据量的读请求的第一总线上的第一设备的系统和方法。所述系统和方法还包括响应于所述桥接器接收所述读请求，检测代表所述第一设备从所述第二设备请求所述数据的第一部分的桥，其中所述桥将所述第一总线耦合到所述第二总线。此外，系统和方法包括触发桥接器代表第一设备请求附加的数据部分。

7. 发明申请

US20080157840A1 Systems and Methods for Adding a Delay to a Signal 有权
标题翻译：向信号添加延迟的系统和方法
公开(公告)号：US20080157840A1
公开(公告)日：2008-07-03
申请号：US11967079
申请日：2007-12-29
申请人： Roland Sperlich , Amer Hani Atrash
发明人： Roland Sperlich , Amer Hani Atrash
IPC分类号： H03L7/00
CPC分类号： G06F1/10 , H03L7/07 , H03L7/0812
摘要： Systems and methods for transmitting a signal having a desired phase at the device are disclosed. The systems and methods further include determining a signal path length to a device over a transmission line and adding a delay to a signal to be transmitted over the transmission line. The determination is made in response to determining the path length to the device.
摘要翻译：公开了用于在设备处发送具有期望相位的信号的系统和方法。所述系统和方法还包括通过传输线确定到设备的信号路径长度，并将延迟添加到要通过传输线传输的信号。响应于确定到设备的路径长度而进行确定。

8. 发明申请

US20070177411A1 Diode bridge configurations for increasing current in a distributed power network 有权
标题翻译：用于在分布式电力网络中增加电流的二极管桥结构
公开(公告)号：US20070177411A1
公开(公告)日：2007-08-02
申请号：US11657151
申请日：2007-01-24
申请人： Jean Picard
发明人： Jean Picard
IPC分类号： H02J3/36
CPC分类号： H04L12/10
摘要： One embodiment of the present invention includes a communication network comprises a communication cable having a first wire pair and a second wire pair that both extend between a first end and a second end of the communication cable. The network also comprises at least one power source configured to provide a first supply current through the first wire pair and a second supply current through the second wire pair at the first end of the communication cable. The first supply current and the second supply current can be substantially equal. The network also comprises a first diode bridge and a second diode bridge coupled to the second end of the communication cable and configured to combine the first and second supply currents to provide a combined supply current. The network further comprises a powered device configured to receive the combined supply current.
摘要翻译：本发明的一个实施例包括通信网络，其包括通信电缆，该通信电缆具有在通信电缆的第一端和第二端之间延伸的第一线对和第二线对。网络还包括被配置为提供通过第一线对的第一电源电流和在通信电缆的第一端处通过第二线对的第二电源电流的至少一个电源。第一电源电流和第二电源电流可以基本相等。网络还包括耦合到通信电缆的第二端的第一二极管桥和第二二极管桥，并且被配置为组合第一和第二电源电流以提供组合的电源电流。网络还包括被配置为接收组合的电源电流的供电设备。

9. 发明申请

US20070168801A1 Adapting scan architectures for low power operation 有权
标题翻译：适应低功耗操作的扫描体系结构
公开(公告)号：US20070168801A1
公开(公告)日：2007-07-19
申请号：US11535714
申请日：2006-09-27
申请人： Lee Whetsel
发明人： Lee Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/31721 , G01R31/31723 , G01R31/3177 , G01R31/318575 , G01R31/318577
摘要： Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.
摘要翻译：扫描架构通常用于测试集成电路中的数字电路。本发明描述了一种使常规扫描架构适应于低功率扫描架构的方法。低功耗扫描架构保持常规扫描架构的测试时间，同时要求比传统扫描架构明显更低的运行能力。低功耗扫描架构对于IC /模具制造商是有利的，因为它允许并行测试嵌入在IC /管芯中的更多数量的电路（例如DSP或CPU核心电路），而不会消耗IC /管芯内的太多功率。由于低功耗扫描架构降低了测试功耗，因此可以使用传统的扫描架构在以前可能的同时测试晶片上的更多裸片。这允许减少晶片测试时间，这降低了晶片上每个芯片的制造成本。

10. 发明授权

US06898678B1 Shared memory with programmable size 有权
标题翻译：具有可编程大小的共享内存
公开(公告)号：US06898678B1
公开(公告)日：2005-05-24
申请号：US09591615
申请日：2000-06-09
申请人： Laurent Six , Armelle Laine , Daniel Mazzocco , Gerald Ollivier
发明人： Laurent Six , Armelle Laine , Daniel Mazzocco , Gerald Ollivier
IPC分类号： G06F13/16 , G06F13/28 , G09F12/06
CPC分类号： G06F13/1694 , G06F13/28 , Y02D10/14
摘要： A digital system is provided with a memory (42) that can be shared by two or more data requestors (10, 20). Two modes of access are provided. In a shared access memory (SAM) access mode, all of the data requestors can sequentially access the memory. In a host only memory (HOM) access mode, a portion (42a) of the memory is connected directly to one of the requestors, such, as a host processor (10), so that high bandwidth transfers can be performed. A portion (42b) that is not selected to be in HOM mode can be accessed by other requestors or shut down to save power. The size (S1) of the portion of memory selected for HOM mode is selected to match the requirements of a given application and can be changed by writing a size value to a register.
摘要翻译：数字系统具有可由两个或多个数据请求器（10,20）共享的存储器（42）。提供了两种访问方式。在共享访问存储器（SAM）访问模式中，所有数据请求者可以顺序访问存储器。在仅主机存储器（HOM）访问模式中，存储器的一部分（42a）直接连接到请求者之一，诸如作为主机处理器（10），从而可以执行高带宽传输。未选择为HOM模式的部分（42b）可被其他请求者访问或关闭以节省电力。选择用于HOM模式的存储器部分的大小（S1）被选择以匹配给定应用的要求，并且可以通过向寄存器写入大小值来改变。

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