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1. 发明授权

US07015077B1 Varied trench depth for thyristor isolation 失效
标题翻译：用于晶闸管隔离的不同沟槽深度
公开(公告)号：US07015077B1
公开(公告)日：2006-03-21
申请号：US10970085
申请日：2004-10-21
申请人： Andrew Horch , Scott Robins
发明人： Andrew Horch , Scott Robins
IPC分类号： H01L21/332
CPC分类号： H01L29/74 , H01L21/76224 , H01L21/763 , H01L27/0817 , H01L29/0649
摘要： A semiconductor device is formed having a thyristor and trench arranged to electrically insulate an emitter region of the thyristor from another circuit structure. In one example embodiment of the present invention, a trench having a bottom portion with two different trench depths is etched in the substrate. A thyristor is formed having a control port in a trench and having an emitter region adjacent to the trench and below an upper surface of the substrate. A deeper portion of the trench electrically insulates the emitter region from the other circuit structure. The control port is capacitively coupled to the thyristor and to the other circuit structure (e.g., in response to at least one edge of a voltage pulse applied thereto). In one implementation, the trench further includes an emitter-access connector extending from the emitter region to an upper surface of the substrate. These approaches are also useful in high-density circuit applications, such as memory applications, where the semiconductor device is formed in close proximity with other circuitry, such as with other thyristors. In addition, the isolation approach is useful for applications where a cathode-down thyristor is used, such as when it is desirable to form the thyristor control port near a bottom portion of the thyristor. Moreover, the approaches discussed herein are useful for electrically isolating various portions of the semiconductor device using a relatively limited number of etching steps.
摘要翻译：形成半导体器件，其具有晶闸管和沟槽，其布置成将晶闸管的发射极区域与另一个电路结构电绝缘。在本发明的一个示例性实施例中，在衬底中蚀刻具有具有两个不同沟槽深度的底部的沟槽。晶闸管形成为具有沟槽中的控制端口，并且具有与沟槽相邻的发射极区域以及衬底的上表面下方。沟槽的较深部分将发射极区域与另一个电路结构电绝缘。控制端口电容耦合到晶闸管和另一电路结构（例如，响应于施加到晶闸管的电压脉冲的至少一个边缘）。在一个实施方式中，沟槽还包括从发射极区延伸到衬底的上表面的发射器 - 接入连接器。这些方法在诸如存储器应用的高密度电路应用中也是有用的，其中半导体器件形成在与其它电路（例如与其他晶闸管）相近的位置。此外，隔离方法对于使用阴极 - 下降晶闸管的应用是有用的，例如当期望在晶闸管的底部附近形成晶闸管控制端口时。此外，本文讨论的方法可用于使用相对有限数量的蚀刻步骤电绝缘半导体器件的各个部分。

2. 发明授权

US06975260B1 Geometric D/A converter for a delay-locked loop 失效
标题翻译：用于延迟锁定环路的几何D / A转换器
公开(公告)号：US06975260B1
公开(公告)日：2005-12-13
申请号：US10986707
申请日：2004-11-12
申请人： Shahram Abdollahi-Alibeik , Chaofeng Huang
发明人： Shahram Abdollahi-Alibeik , Chaofeng Huang
IPC分类号： H03M1/66 , H03M1/68 , H03M1/74
CPC分类号： H03M1/68 , H03M1/745
摘要： A geometric DAC architecture includes a series of substantially identical sub-DACs, each sub-DAC having n taps. The sub-DACs are fed from a bias-DAC having m=(total number of taps needed)/n taps. The output of each of the m taps is increased geometrically at a rate of kn. The geometric DAC architecture control lines desirably require only (m+n) taps compared with (m×n) taps for the simpler more conventional approach. Further, the geometric DAC architecture requires less real estate than the simpler more conventional approach, is easy to expand because it is modular, and generates an output current that is always monotonic, regardless of errors in transistor sizes and PVT variations. The n tap control lines are coded by alternately inverting n control line inputs between sub-DACs such that any state transition associated with the geometric DAC occurs with only one bit change in each of the control lines.
摘要翻译：几何DAC架构包括一系列基本相同的子DAC，每个子DAC具有n个抽头。子DAC从具有m =（所需抽头总数）/ n抽头的偏置DAC馈送。 m个抽头中的每一个的输出以几何的方式以k 的速率增加。对于更简单的更传统的方法，几何DAC架构控制线期望仅需要（m + n）个抽头与（m×n）抽头相比较。此外，几何DAC架构比简单的更传统的方法需要更少的空间，由于它是模块化而容易扩展，并且产生总是单调的输出电流，而不管晶体管尺寸和PVT变化中的错误。通过在子DAC之间交替地反转n个控制线输入来编码n个抽头控制线，使得与几何DAC相关联的任何状态转换在每个控制线中仅发生一个位改变。

3. 发明授权

US06958931B1 Bit line control and sense amplification for TCCT-based memory cells 失效
标题翻译：基于TCCT的存储单元的位线控制和读出放大
公开(公告)号：US06958931B1
公开(公告)日：2005-10-25
申请号：US10209116
申请日：2002-07-30
申请人： Sei-Seung Yoon , Seong-Ook Jung
发明人： Sei-Seung Yoon , Seong-Ook Jung
IPC分类号： G11C11/39 , G11C11/00
CPC分类号： G11C11/39
摘要： A circuit and a method are provided for facilitating control of bit lines in preparation for, or during, sense amplification of data signals from thinly capacitively-coupled thyristor (“TCCT”)-based memory cells. In accordance with a specific embodiment, a circuit and method are designed, among other things, to effectively minimize power consumption by memory cells and to increase speed and reliability of sense amplification. In another specific embodiment, the circuit and method are directed to TCCT-based memory cells.
摘要翻译：提供了一种电路和方法，用于促进对位线的控制，以准备或在其期间从来自薄电容耦合晶闸管（“TCCT”）的存储器单元的数据信号的感测放大。根据具体实施例，除其他之外，设计电路和方法以有效地最小化存储器单元的功耗并增加感测放大的速度和可靠性。在另一具体实施例中，电路和方法针对基于TCCT的存储器单元。

4. 发明授权

US06937085B1 Sense amplifier based voltage comparator 失效
标题翻译：基于感应放大器的电压比较器
公开(公告)号：US06937085B1
公开(公告)日：2005-08-30
申请号：US10423767
申请日：2003-04-25
申请人： Tapan Samaddar
发明人： Tapan Samaddar
IPC分类号： G11C7/06 , H03K3/356 , H03K17/296 , H03H11/26
CPC分类号： G11C7/062 , H03K3/356139 , Y10T307/549
摘要： The voltage comparator of the present invention comprises a sense amplifier connected to a latch. The sense amplifier has a first input terminal for connecting to the input voltage under consideration and a second input terminal for connecting to the reference voltage. The sense amplifier generates two voltages of opposite logic values (i.e., high or low). A latch accepts these two voltages and generates an output voltage that is indicative of whether the voltage under consideration is higher or lower than the reference voltage. In another embodiment, a signal conditioning circuit is used to reduce the transients in the input voltage under consideration and perform level shifting function.
摘要翻译：本发明的电压比较器包括连接到锁存器的读出放大器。读出放大器具有用于连接到考虑的输入电压的第一输入端子和用于连接到参考电压的第二输入端子。读出放大器产生相反逻辑值的两个电压（即，高或低）。闩锁接受这两个电压，并产生一个输出电压，该输出电压指示所考虑的电压是否高于或低于参考电压。在另一个实施例中，使用信号调理电路来减少所考虑的输入电压的瞬变并执行电平转换功能。

5. 发明授权

US06911680B1 Self-aligned thin capacitively-coupled thyristor structure 失效
标题翻译：自对准薄电容耦合晶闸管结构
公开(公告)号：US06911680B1
公开(公告)日：2005-06-28
申请号：US10890031
申请日：2004-07-13
申请人： Andrew Horch , Scott Robins , Farid Nemati
发明人： Andrew Horch , Scott Robins , Farid Nemati
IPC分类号： H01L21/331 , H01L27/11 , H01L29/74 , H01L29/745
CPC分类号： H01L29/66242 , H01L27/11 , H01L29/7436 , H01L29/7455
摘要： A semiconductor memory device having a thyristor is manufactured in a manner that makes possible self-alignment of one or more portions of the thyristor. According to an example embodiment of the present invention, a gate is formed over a first portion of doped substrate. The gate is used to mask a portion of the doped substrate and a second portion of the substrate is doped before or after a spacer is formed. After the second portion of the substrate is doped, the spacer is then formed adjacent to the gate and used to mask the second portion of the substrate while a third portion of the substrate is doped. The gate and spacer are thus used to form self-aligned doped portions of the substrate, wherein the first and second portions form base regions and the third portion form an emitter region of a thyristor. In another implementation, the spacer is also adapted to prevent formation of salicide on the portion of the thyristor beneath the spacer, self-aligning the salicide to the junction between the second and third portions. In addition, dimensions such as width and other characteristics of the doped portions that are used to form a thyristor can be controlled without necessarily using a separate mask.
摘要翻译：制造具有晶闸管的半导体存储器件以能够使晶闸管的一个或多个部分自对准的方式。根据本发明的示例性实施例，在掺杂衬底的第一部分上形成栅极。栅极用于掩模掺杂衬底的一部分，并且衬底的第二部分在形成间隔物之前或之后被掺杂。在衬底的第二部分被掺杂之后，然后在衬底的第三部分被掺杂的同时，将衬底形成为邻近栅极并用于掩蔽衬底的第二部分。因此，栅极和间隔物用于形成衬底的自对准掺杂部分，其中第一和第二部分形成基极区，第三部分形成晶闸管的发射极区。在另一实施方案中，间隔物还适于防止在间隔物下方的可控硅部分上形成自对准硅化物，使自对准硅化物与第二和第三部分之间的连接处。此外，可以控制用于形成晶闸管的掺杂部分的宽度和其它特性的尺寸，而不必使用单独的掩模。

6. 发明授权

US06891205B1 Stability in thyristor-based memory device 失效
标题翻译：基于晶闸管的存储器件的稳定性
公开(公告)号：US06891205B1
公开(公告)日：2005-05-10
申请号：US10666220
申请日：2003-09-19
申请人： Hyun-Jin Cho , Farid Nemati , Scott Robins
发明人： Hyun-Jin Cho , Farid Nemati , Scott Robins
IPC分类号： G11C11/39 , H01L29/74 , H01L29/749
CPC分类号： H01L29/749 , G11C11/39 , H01L29/7436
摘要： A semiconductor device having a thyristor-based memory device exhibits improved stability under adverse operating conditions related to temperature, noise, electrical disturbances and light. In one particular example embodiment of the present invention, a semiconductor device includes a thyristor-based memory device that uses a shunt that effects a leakage current in the thyristor. The thyristor includes a capacitively-coupled control port and anode and cathode end portions. Each of the end portions has an emitter region and an adjacent base region. In one implementation, the current shunt is located between the emitter and base region of one of the end portions of the thyristor and is configured and arranged to shunt low-level current therebetween. In connection with an example embodiment, it has been discovered that shunting current in this manner improves the ability of the device to operate under adverse conditions that would, absent the shunt, result in inadvertent turn on, while keeping the standby current of the memory device to an acceptably low level.
摘要翻译：具有基于晶闸管的存储器件的半导体器件在与温度，噪声，电扰动和光线相关的不利操作条件下表现出改进的稳定性。在本发明的一个具体示例实施例中，半导体器件包括基于晶闸管的存储器件，其使用在晶闸管中产生漏电流的分流器。晶闸管包括电容耦合控制端口和阳极和阴极端部分。每个端部具有发射极区域和相邻的基极区域。在一个实施方案中，电流分流器位于晶闸管的一个端部的发射极和基极区域之间，并且被配置和布置成在它们之间分流低电平电流。结合示例性实施例，已经发现，以这种方式分流电流提高了器件在不利条件下操作的能力，这种不利条件将在不存在分流的情况下导致无意中导通，同时保持存储器件的待机电流达到可接受的低水平。

7. 发明授权

US06888177B1 Increased base-emitter capacitance 失效
标题翻译：增加基极 - 发射极电容
公开(公告)号：US06888177B1
公开(公告)日：2005-05-03
申请号：US10253350
申请日：2002-09-24
申请人： Farid Nemati , Scott Robins , Andrew Horch
发明人： Farid Nemati , Scott Robins , Andrew Horch
IPC分类号： H01L21/332 , H01L21/84 , H01L27/108 , H01L27/12 , H01L29/417 , H01L29/74
CPC分类号： H01L27/108 , H01L21/84 , H01L23/535 , H01L27/1203 , H01L29/41716 , H01L29/66393 , H01L2924/0002 , H01L2924/00
摘要： A thyristor-based semiconductor device exhibits a relatively increased base-emitter capacitance. According to an example embodiment of the present invention, the junction area between a base region and an adjacent emitter region of a thyristor is increased, relative to the junction area between other regions in the thyristor. In one implementation, the base region is formed extending on two sides of the emitter region. In another implementation, the thyristor is formed on a buried insulator layer of a silicon-on-insulator (SOI) structure, with the base region having a first portion laterally adjacent to the emitter region and having a second portion between the emitter region and the buried insulator.
摘要翻译：基于晶闸管的半导体器件表现出相对增加的基极 - 发射极电容。根据本发明的示例性实施例，晶闸管的基极区域和相邻发射极区域之间的结面积相对于晶闸管中的其它区域之间的接合面积增加。在一个实施方式中，形成在发射极区域的两侧上延伸的基极区域。在另一种实施方式中，晶闸管形成在绝缘体上硅（SOI）结构的掩埋绝缘体层上，其中基极区域具有与发射极区域相邻的第一部分，并且在发射极区域和发射极区域之间具有第二部分埋绝缘体。

8. 发明申请

US20060139996A1 Dynamic data restore in thyristor-based memory device 失效
公开(公告)号：US20060139996A1
公开(公告)日：2006-06-29
申请号：US11361334
申请日：2006-02-24
申请人： Farid Nemati , Hyun-jin Cho , Robert Igehy
发明人： Farid Nemati , Hyun-jin Cho , Robert Igehy
IPC分类号： G11C11/34
CPC分类号： G11C11/39
摘要： A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the internal positive feedback loop in the thyristor is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.

9. 发明授权

US07054191B1 Method and system for writing data to memory cells 有权
标题翻译：将数据写入存储单元的方法和系统
公开(公告)号：US07054191B1
公开(公告)日：2006-05-30
申请号：US10860194
申请日：2004-06-03
申请人： Rajesh Narendra Gupta , Scott Robins
发明人： Rajesh Narendra Gupta , Scott Robins
IPC分类号： G11C11/39 , G11C11/34
CPC分类号： G11C11/39
摘要： A first and a second set of memory cells are connected to the same first word line and second word line. At the commencement of data writing, the first word line is set up. The first set of memory cells is read and temporarily stored into a buffer. At about the same time, the bit lines of the second set of memory cells is set up. After completion of reading of the first set of memory cells, the bit lines of this set of memory cells are set up (while the setting up of the bit lines of the second set of memory cells continues). After the bit lines of both sets of memory cells are set up, the second word line is pulsed. At this time, written into both sets of memory cells begins, which comprises data previously read from the first set of memory cells and new data to be written into the second set of memory cells. It is found that this method reduces the overall write time.
摘要翻译：第一和第二组存储器单元连接到相同的第一字线和第二字线。在数据写入开始时，第一个字线被设置。第一组存储单元读取并临时存储到缓冲器中。大约在同一时间，第二组存储器单元的位线被建立。在完成第一组存储单元的读取之后，建立该组存储器单元的位线（同时第二组存储器单元的位线的设置继续）。在两组存储器单元的位线被建立之后，第二字线被脉冲。此时，开始写入两组存储器单元，其包括先前从第一组存储器单元读取的数据和要写入第二组存储器单元的新数据。发现这种方法减少了整个写入时间。

10. 发明授权

US07006398B1 Single data line sensing scheme for TCCT-based memory cells 失效
标题翻译：基于TCCT的存储单元的单数据线感测方案
公开(公告)号：US07006398B1
公开(公告)日：2006-02-28
申请号：US10977309
申请日：2004-10-29
申请人： Sei-Seung Yoon , Jin-Man Han , Seong-Ook Jung
发明人： Sei-Seung Yoon , Jin-Man Han , Seong-Ook Jung
IPC分类号： G11C11/00
CPC分类号： H01L27/11 , G11C11/39
摘要： A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as VDD. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.
摘要翻译：本文公开了一种包括用于解析由存储器单元产生的数据信号的读出放大器的感测电路。感测电路包括用于接收数据信号的位线，耦合到位线并被配置为对位线预充电的第一预充电器件，用于提供耦合到位线的偏置并被配置为提供偏置到位线，以及被配置为至少一个预定电平的参考节点。在一个实施例中，预定电平等于诸如地电位的低电位，而在另一实施例中等于诸如V DD的高电位。一个或多个开关装置允许激活或去激活预充电装置，允许将位线预充电到特定电位，感测电路快速而准确地确定逻辑状态“1”或“0”是否为应用于位线。

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