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1. 发明授权

US06975260B1 Geometric D/A converter for a delay-locked loop 失效
标题翻译：用于延迟锁定环路的几何D / A转换器
公开(公告)号：US06975260B1
公开(公告)日：2005-12-13
申请号：US10986707
申请日：2004-11-12
申请人： Shahram Abdollahi-Alibeik , Chaofeng Huang
发明人： Shahram Abdollahi-Alibeik , Chaofeng Huang
IPC分类号： H03M1/66 , H03M1/68 , H03M1/74
CPC分类号： H03M1/68 , H03M1/745
摘要： A geometric DAC architecture includes a series of substantially identical sub-DACs, each sub-DAC having n taps. The sub-DACs are fed from a bias-DAC having m=(total number of taps needed)/n taps. The output of each of the m taps is increased geometrically at a rate of kn. The geometric DAC architecture control lines desirably require only (m+n) taps compared with (m×n) taps for the simpler more conventional approach. Further, the geometric DAC architecture requires less real estate than the simpler more conventional approach, is easy to expand because it is modular, and generates an output current that is always monotonic, regardless of errors in transistor sizes and PVT variations. The n tap control lines are coded by alternately inverting n control line inputs between sub-DACs such that any state transition associated with the geometric DAC occurs with only one bit change in each of the control lines.
摘要翻译：几何DAC架构包括一系列基本相同的子DAC，每个子DAC具有n个抽头。子DAC从具有m =（所需抽头总数）/ n抽头的偏置DAC馈送。 m个抽头中的每一个的输出以几何的方式以k 的速率增加。对于更简单的更传统的方法，几何DAC架构控制线期望仅需要（m + n）个抽头与（m×n）抽头相比较。此外，几何DAC架构比简单的更传统的方法需要更少的空间，由于它是模块化而容易扩展，并且产生总是单调的输出电流，而不管晶体管尺寸和PVT变化中的错误。通过在子DAC之间交替地反转n个控制线输入来编码n个抽头控制线，使得与几何DAC相关联的任何状态转换在每个控制线中仅发生一个位改变。

2. 发明授权

US06734815B1 Geometric D/A converter for a delay-locked loop 失效
标题翻译：用于延迟锁定环路的几何D / A转换器
公开(公告)号：US06734815B1
公开(公告)日：2004-05-11
申请号：US10396884
申请日：2003-03-25
申请人： Shahram Abdollahi-Alibeik , Chaofeng Huang
发明人： Shahram Abdollahi-Alibeik , Chaofeng Huang
IPC分类号： H03M166
CPC分类号： H03M1/68 , H03M1/745
摘要： A geometric DAC architecture includes a series of substantially identical sub-DACs, each sub-DAC having n taps. The sub-DACs are fed from a bias-DAC having m=(total number of taps needed)/n taps. The output of each of the m taps is increased geometrically at a rate of kn. The geometric DAC architecture control lines desirably require only (m+n) taps compared with (m×n) taps for the simpler more conventional approach. Further, the geometric DAC architecture requires less real estate than the simpler more conventional approach, is easy to expand because it is modular, and generates an output current that is always monotonic, regardless of errors in transistor sizes and PVT variations. The n tap control lines are coded by alternately inverting n control line inputs between sub-DACs such that any state transition associated with the geometric DAC occurs with only one bit change in each of the control lines.
摘要翻译：几何DAC架构包括一系列基本相同的子DAC，每个子DAC具有n个抽头。子DAC从具有m =（所需抽头总数）/ n抽头的偏置DAC馈送。每个m个抽头的输出以k 的速率几何地增加。对于更简单的更传统的方法，几何DAC架构控制线期望仅需要（m + n）个抽头与（m×n）抽头相比较。此外，几何DAC架构比简单的更传统的方法需要更少的空间，由于它是模块化而容易扩展，并且产生总是单调的输出电流，而不管晶体管尺寸和PVT变化中的错误。通过在子DAC之间交替地反转n个控制线输入来编码n个抽头控制线，使得与几何DAC相关联的任何状态转换在每个控制线中仅发生一个位改变。

3. 发明授权

US06947349B1 Apparatus and method for producing an output clock pulse and output clock generator using same 失效
标题翻译：用于产生输出时钟脉冲和使用其的输出时钟发生器的装置和方法
公开(公告)号：US06947349B1
公开(公告)日：2005-09-20
申请号：US10654258
申请日：2003-09-03
申请人： Shahram Abdollahi-Alibeik , Chaofeng Huang
发明人： Shahram Abdollahi-Alibeik , Chaofeng Huang
IPC分类号： G11C8/00 , G11C11/419 , G11C29/02
CPC分类号： G11C29/12015 , G11C11/41 , G11C11/419 , G11C29/02 , G11C29/028 , G11C29/1201 , G11C29/50012
摘要： A method and apparatus generates output clock pulses, having leading and trailing edges that are adjusted in a pulse forming processor, according to the relative phase of an output clock and output data. Dynamic adjustment of the leading and trailing edges of output clock pulses improves the performance of high-speed devices significantly.
摘要翻译：一种方法和装置根据输出时钟和输出数据的相对相位产生具有在脉冲形成处理器中调整的前沿和后沿的输出时钟脉冲。输出时钟脉冲的前沿和后沿的动态调整显着提高了高速器件的性能。

4. 发明授权

US07464282B1 Apparatus and method for producing dummy data and output clock generator using same 失效
标题翻译：用于产生伪数据的装置和方法以及使用其的输出时钟发生器
公开(公告)号：US07464282B1
公开(公告)日：2008-12-09
申请号：US10654322
申请日：2003-09-03
申请人： Shahram Abdollahi-Alibeik , Chaofeng Huang
发明人： Shahram Abdollahi-Alibeik , Chaofeng Huang
IPC分类号： G06F1/12
CPC分类号： G11C7/22 , G11C7/222 , G11C2207/2254 , H03L7/0814
摘要： An apparatus and method for producing dummy data is based on timing paths co-located with the address/data paths of the memory. An output clock generator uses the dummy data. The technique for producing dummy data is particularly important for memory systems in which the output of memory cells do not normally provide large voltage swings, making them less practical for self timing approaches to dummy data generation.
摘要翻译：用于产生伪数据的装置和方法基于与存储器的地址/数据路径共同定位的定时路径。输出时钟发生器使用虚拟数据。用于产生虚拟数据的技术对于其中存储器单元的输出通常不提供大的电压摆动的存储器系统是特别重要的，使得它们对于伪数据生成的自定时方法不太实用。

5. 发明授权

US07089439B1 Architecture and method for output clock generation on a high speed memory device 失效
标题翻译：用于在高速存储器件上产生输出时钟的架构和方法
公开(公告)号：US07089439B1
公开(公告)日：2006-08-08
申请号：US10654358
申请日：2003-09-03
申请人： Shahram Abdollahi-Alibeik , Chaofeng Huang
发明人： Shahram Abdollahi-Alibeik , Chaofeng Huang
IPC分类号： G06F1/12
CPC分类号： G06F1/10
摘要： An output clock for a memory device having a read latency more than one clock cycle includes a clock generator at a central location on the device. A clock channel couples the clock generator to output structures. A timing path emulates the address/data paths in the memory, and is responsive to an address emulation signal produced by the clock generator to provide dummy data near the output structures. An output clock signal with an adjustable phase and a dummy data reference clock signal on the input of the clock channel are generated. A phase detector near the output structures, determines whether the output clock is early, late or on time with respect to the dummy data. Logic signals are produced at the phase detector, and returned to the clock generator for adjusting the relative phase of the output clock signal.
摘要翻译：具有超过一个时钟周期的读等待时间的存储器件的输出时钟包括在器件上的中心位置处的时钟发生器。时钟信道将时钟发生器耦合到输出结构。定时路径模拟存储器中的地址/数据路径，并且响应于由时钟发生器产生的地址仿真信号，以在输出结构附近提供伪数据。产生在时钟通道的输入端具有可调节相位和伪数据参考时钟信号的输出时钟信号。在输出结构附近的相位检测器确定输出时钟是否相对于虚拟数据的早，晚或准时。逻辑信号在相位检测器处产生，并返回到时钟发生器，用于调节输出时钟信号的相对相位。

6. 发明授权

US06891774B1 Delay line and output clock generator using same 失效
标题翻译：延迟线和输出时钟发生器使用相同
公开(公告)号：US06891774B1
公开(公告)日：2005-05-10
申请号：US10654561
申请日：2003-09-03
申请人： Shahram Abdollahi-Alibeik , Chaofeng Huang
发明人： Shahram Abdollahi-Alibeik , Chaofeng Huang
IPC分类号： G11C7/22 , G11C11/419 , G11C29/02 , H03K5/00 , H03K5/13 , H03L7/081 , G11C8/00
CPC分类号： G11C7/22 , G11C7/222 , G11C11/419 , G11C29/02 , G11C29/028 , G11C29/50012 , H03K5/133 , H03K2005/00032 , H03L7/0812
摘要： A delay line for an adjustable, high speed clock generator is based on two-stage multiplexing, in which for all pairs of adjacent taps, a change from a current tap to an adjacent tap in the pair is executed by switching only one of the first stage and second stage multiplexers. Control signals are generated for the first and second stage multiplexers by logic based on bidirectional shift registers. The delay line is suitable for generation of an output clock having an adjustable phase, allowing for smooth, glitch-free adjustment over a large range of phases.
摘要翻译：用于可调节的高速时钟发生器的延迟线基于两级复用，其中对于所有相邻抽头对，通过仅切换第一级中的一个来执行从该对中的当前抽头到相邻抽头的改变阶段和第二阶段多路复用器。通过基于双向移位寄存器的逻辑为第一和第二级多路复用器产生控制信号。延迟线适用于产生具有可调节相位的输出时钟，允许在大范围的相位上平滑，无故障地调整。

7. 发明授权

US06819278B1 Geometric D/A converter for a delay-locked loop 失效
公开(公告)号：US06819278B1
公开(公告)日：2004-11-16
申请号：US10808148
申请日：2004-03-24
申请人： Shahram Abdollahi-Alibeik , Chaofeng Huang
发明人： Shahram Abdollahi-Alibeik , Chaofeng Huang
IPC分类号： H03M166
CPC分类号： H03M1/68 , H03M1/745
摘要： A geometric DAC architecture includes a series of substantially identical sub-DACs, each sub-DAC having n taps. The sub-DACs are fed from a bias-DAC having m=(total number of taps needed)/n taps. The output of each of the m taps is increased geometrically at a rate of kn. The geometric DAC architecture control lines desirably require only (m+n) taps compared with (m×n) taps for the simpler more conventional approach. Further, the geometric DAC architecture requires less real estate than the simpler more conventional approach, is easy to expand because it is modular, and generates an output current that is always monotonic, regardless of errors in transistor sizes and PVT variations. The n tap control lines are coded by alternately inverting n control line inputs between sub-DACs such that any state transition associated with the geometric DAC occurs with only one bit change in each of the control lines.

8. 发明申请

US20120147944A1 HIGH RESOLUTION OUTPUT DRIVER 有权
标题翻译：高分辨率输出驱动器
公开(公告)号：US20120147944A1
公开(公告)日：2012-06-14
申请号：US13391383
申请日：2010-09-14
申请人： Amir Amirkhany , Chaofeng Huang , Kambiz Kaviani , Wayne D. Dettloof , Kun-Yung Chang
发明人： Amir Amirkhany , Chaofeng Huang , Kambiz Kaviani , Wayne D. Dettloof , Kun-Yung Chang
IPC分类号： H04L27/01
CPC分类号： H03K19/0005 , H03K19/017581 , H03M1/1061 , H03M1/745 , H04L25/0278 , H04L25/0288 , H04L25/03343
摘要： High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested “DAC within a DAC” arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.
摘要翻译：具有相对较少数量的子驱动器分支或切片的高分辨率输出驱动器，每个子驱动器分支或切片具有显着大于量化步长的标称阻抗，并且通过显着小于量化步长的阻抗步长递增地彼此不同。在一个实现中，这种“差分”或“不均匀”子驱动器切片实现n选择k均衡器的相应元件，每个这样的差分子驱动器切片由均匀元件阻抗校准DAC实现。在另一实施方式中，均匀分片均衡器的每个分量由差分片阻抗校准DAC实现，并且在又一实现中，差分片均衡器的每个分量由差分片阻抗校准DAC实现。在一组额外的实施方案中，均衡和阻抗校准功能在各个并行的驱动器分支组中实现，而不是分层实现中嵌套的“DAC内的DAC”布置。通过这种双边安排，避免了均衡器和校准器量化的乘法，从而降低了满足指定范围和分辨率所需的副驱动器片的总数。

9. 发明授权

US06977980B2 Timing synchronization methods and systems for transmit parallel interfaces 失效
标题翻译：用于传输并行接口的定时同步方法和系统
公开(公告)号：US06977980B2
公开(公告)日：2005-12-20
申请号：US09942198
申请日：2001-08-29
申请人： Kun-Yung Ken Chang , Chaofeng Huang
发明人： Kun-Yung Ken Chang , Chaofeng Huang
IPC分类号： H04L7/02 , H04L7/00
CPC分类号： H04L7/02
摘要： Transmit parallel interfaces and methods are provided in which a clock signal is generated that maximizes the setup and hold window of input data. In at least some embodiments, a divider circuit provides a clock signal in one clock domain that has a rising edge located very close to the falling edge of a system clock in another clock domain.
摘要翻译：提供了发送并行接口和方法，其中产生使输入数据的建立和保持窗口最大化的时钟信号。在至少一些实施例中，分频器电路在一个时钟域提供时钟信号，该时钟信号具有非常接近另一个时钟域中系统时钟下降沿的上升沿。

10. 发明申请

US20120187978A1 Methods and Circuits for Calibrating Multi-Modal Termination Schemes 有权
标题翻译：用于校准多模式终端方案的方法和电路
公开(公告)号：US20120187978A1
公开(公告)日：2012-07-26
申请号：US13349226
申请日：2012-01-12
申请人： Hajee Mohammed Shuaeb Fazeel , Amir Amirkhany , Gundlapalli Shanmukha Srinivas , Chaofeng Huang
发明人： Hajee Mohammed Shuaeb Fazeel , Amir Amirkhany , Gundlapalli Shanmukha Srinivas , Chaofeng Huang
IPC分类号： H03K19/003
CPC分类号： H03K19/017545 , G11C29/025 , G11C29/028 , H03K19/018514 , H03K19/018564
摘要： Disclosed are methods and circuits that support different on-die termination (ODT) schemes for a plurality of signaling schemes using a relatively small number of external calibration pads. These methods and circuits develop control signals for calibrating any of multiple termination schemes that might be used by associated communication circuits. The ODT control circuits, entirely or predominantly instantiated on-die, share circuit resources employed in support of the different termination schemes to save die area.
摘要翻译：公开了使用相对较少数量的外部校准焊盘来支持用于多个信令方案的不同的管芯端接（ODT）方案的方法和电路。这些方法和电路开发用于校准可能由相关联的通信电路使用的多个终止方案中的任何一个的控制信号。 ODT控制电路，完全或主要实例化的裸片，共享用于支持不同终端方案的电路资源，以节省芯片面积。

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