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1. 发明授权

US06965129B1 Thyristor-based device having dual control ports 失效
标题翻译：具有双控制端口的基于晶闸管的装置
公开(公告)号：US06965129B1
公开(公告)日：2005-11-15
申请号：US10288953
申请日：2002-11-06
申请人： Andrew Horch , Scott Robins , Farid Nemati
发明人： Andrew Horch , Scott Robins , Farid Nemati
IPC分类号： G11C11/39 , H01L21/8239 , H01L27/08 , H01L27/102 , H01L27/105 , H01L27/108 , H01L29/74
CPC分类号： G11C11/39 , H01L27/1025 , H01L27/1027 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L29/7436
摘要： Switching operations, such as those used in memory devices, are enhanced using a thyristor-based semiconductor device adapted to switch between a blocking state and a conducting state. According to an example embodiment of the present invention, a thyristor-based semiconductor device includes a thyristor having first and second base regions coupled between first and second emitter regions, respectively. A first control port capacitively couples a first signal to the first base region, and a second control port capacitively couples a second signal to the second base region. Each of the first and second signals have a charge that is opposite in polarity, and the opposite polarity signals effect the switching of the thyristor at a lower power, relative to the power that would be required to switch the thyristor having only one control port. In this manner, power consumption for a switching operation can be reduced, which is useful, for example, to correspond with reduced power supplied to other devices in a semiconductor device employing the thyristor.
摘要翻译：使用适于在阻塞状态和导通状态之间切换的基于晶闸管的半导体器件来增强诸如存储器件中使用的切换操作。根据本发明的示例性实施例，基于晶闸管的半导体器件包括分别具有耦合在第一和第二发射极区之间的第一和第二基极区域的晶闸管。第一控制端口将第一信号电容耦合到第一基区，并且第二控制端口将第二信号电容耦合到第二基区。第一和第二信号中的每一个具有极性相反的电荷，相反的极性信号相对于仅具有一个控制端口的晶闸管所需的功率，以较低的功率影响晶闸管的开关。以这种方式，可以减少用于开关操作的功耗，这对于例如提供给采用晶闸管的半导体器件中的其它器件的降低的功率是有用的。

2. 发明授权

US06872602B1 Carrier coupler for thyristor-based semiconductor device 失效
标题翻译：用于晶闸管的半导体器件的载流子耦合器
公开(公告)号：US06872602B1
公开(公告)日：2005-03-29
申请号：US10785166
申请日：2004-02-23
申请人： Farid Nemati , Badredin Fatemizadeh , Andrew Horch , Scott Robins
发明人： Farid Nemati , Badredin Fatemizadeh , Andrew Horch , Scott Robins
IPC分类号： H01L21/8242 , H01L21/8244 , H01L27/08 , H01L27/108 , H01L27/11 , H01L29/417 , H01L29/74 , H01L21/332
CPC分类号： H01L29/41716 , H01L27/0817 , H01L27/108 , H01L27/10844 , H01L27/11 , H01L29/74
摘要： Switching times of a thyristor-based semiconductor device are improved by enhancing carrier drainage from a buried thyristor-emitter region. According to an example embodiment of the present invention, a conductive contact extends to a doped well region buried in a substrate and is adapted to drain carriers therefrom. The device includes a thyristor body having at least one doped emitter region buried in the doped well region. A conductive thyristor control port is adapted to capacitively couple to the thyristor body and to control current flow therein. With this approach, the thyristor can be rapidly switched between resistance states, which has been found to be particularly useful in high-speed data latching implementations including but not limited to memory cell applications.
摘要翻译：通过增强从掩埋晶闸管 - 发射极区域的载流子排放，可以改善晶闸管基半导体器件的开关时间。根据本发明的示例性实施例，导电接触延伸到掩埋在衬底中的掺杂阱区，并且适于从其引出载流子。该器件包括晶体管本体，其具有埋在掺杂阱区中的至少一个掺杂射极区。导电晶闸管控制端口适于电容耦合到晶闸管主体并控制其中的电流。通过这种方法，晶闸管可以在电阻状态之间快速切换，这已经被发现在包括但不限于存储器单元应用的高速数据锁存实现中特别有用。

3. 发明授权

US06828176B1 Thyristor having a first emitter with relatively lightly doped portion to the base 失效
标题翻译：晶闸管具有第一发射极，该基极具有相对轻掺杂的部分
公开(公告)号：US06828176B1
公开(公告)日：2004-12-07
申请号：US10650334
申请日：2003-08-28
申请人： Farid Nemati , Scott Robins , Andrew Horch
发明人： Farid Nemati , Scott Robins , Andrew Horch
IPC分类号： H01L21332
CPC分类号： G11C11/39 , H01L27/1203 , H01L29/0834 , H01L29/41725 , H01L29/7436
摘要： A thyristor-based semiconductor device exhibits a relatively increased base-emitter capacitance. According to an example embodiment of the present invention, a base region and an adjacent emitter region of a thyristor are doped such that the emitter region has a lightly-doped portion having a light dopant concentration, relative to the base region. In one embodiment, the thyristor is implemented in a memory circuit, wherein the emitter region is coupled to a reference voltage line and a control port is arranged for capacitively coupling to the thyristor for controlling current flow therein. In another implementation, the thyristor is formed on a buried insulator layer of a silicon-on-insulator (SOI) structure. With these approaches, current flow in the thyristor, e.g., for data storage therein, can be tightly controlled.
摘要翻译：基于晶闸管的半导体器件表现出相对增加的基极 - 发射极电容。根据本发明的示例性实施例，晶闸管的基极区域和相邻发射极区域被掺杂，使得发射极区域相对于基极区域具有光掺杂剂浓度的轻掺杂部分。在一个实施例中，晶闸管实现在存储器电路中，其中发射极区域耦合到参考电压线，并且控制端口布置成电容耦合到晶闸管以控制其中的电流流动。在另一实施方案中，晶闸管形成在绝缘体上硅（SOI）结构的掩埋绝缘体层上。利用这些方法，可以严格控制晶闸管中的电流，例如用于数据存储在其中。

4. 发明授权

US06727528B1 Thyristor-based device including trench dielectric isolation for thyristor-body regions 失效
标题翻译：基于晶闸管的器件包括可晶体管体区域的沟槽介质隔离
公开(公告)号：US06727528B1
公开(公告)日：2004-04-27
申请号：US09815213
申请日：2001-03-22
申请人： Scott Robins , Andrew Horch , Farid Nemati , Hyun-Jin Cho
发明人： Scott Robins , Andrew Horch , Farid Nemati , Hyun-Jin Cho
IPC分类号： H01L2974
CPC分类号： H01L29/66363 , H01L21/76229 , H01L21/76237 , H01L21/763 , H01L27/0617 , H01L27/0817
摘要： A semiconductor device includes a thyristor designed to reduce or eliminate manufacturing and operational difficulties commonly experienced in the formation and operation of NDR devices. According to one example embodiment of the present invention, the semiconductor substrate is trenched adjacent a doped or dopable substrate region, which is formed to include at least two vertically-adjacent thyristor regions of different polarity. A capacitively-coupled control port for the thyristor is coupled to at least one of the thyristor regions. The trench also includes a dielectric material for electrically insulating the vertically-adjacent thyristor regions. The thyristor is electrically connected to other circuitry in the device, such as a transistor, and used to form a device, such as a memory cell.
摘要翻译：半导体器件包括设计用于减少或消除在NDR器件的形成和操作中通常经历的制造和操作困难的晶闸管。根据本发明的一个示例性实施例，半导体衬底在掺杂或可掺杂的衬底区域附近被沟槽，该衬底区域被形成为包括具有不同极性的至少两个垂直相邻的晶闸管区域。用于晶闸管的电容耦合控制端口耦合到至少一个晶闸管区域。沟槽还包括用于使垂直相邻的晶闸管区域电绝缘的电介质材料。晶闸管电连接到器件中的其它电路，例如晶体管，并用于形成诸如存储器单元的器件。

5. 发明授权

US06703646B1 Thyristor with lightly-doped emitter 失效
标题翻译：晶闸管具有在基极上具有相对轻掺杂部分的第一发射极
公开(公告)号：US06703646B1
公开(公告)日：2004-03-09
申请号：US10253363
申请日：2002-09-24
申请人： Farid Nemati , Scott Robins , Andrew Horch
发明人： Farid Nemati , Scott Robins , Andrew Horch
IPC分类号： H01L2974
CPC分类号： G11C11/39 , H01L27/1203 , H01L29/0834 , H01L29/41725 , H01L29/7436
摘要： A thyristor-based semiconductor device exhibits a relatively increased base-emitter capacitance. According to an example embodiment of the present invention, a base region and an adjacent emitter region of a thyristor are doped such that the emitter region has a lightly-doped portion having a light dopant concentration, relative to the base region. In one embodiment, the thyristor is implemented in a memory circuit, wherein the emitter region is coupled to a reference voltage line and a control port is arranged for capacitively coupling to the thyristor for controlling current flow therein. In another implementation, the thyristor is formed on a buried insulator layer of a silicon-on-insulator (SOI) structure. With these approaches, current flow in the thyristor, e.g., for data storage therein, can be tightly controlled.
摘要翻译：基于晶闸管的半导体器件表现出相对增加的基极 - 发射极电容。根据本发明的示例性实施例，晶闸管的基极区域和相邻发射极区域被掺杂，使得发射极区域相对于基极区域具有光掺杂剂浓度的轻掺杂部分。在一个实施例中，晶闸管实现在存储器电路中，其中发射极区域耦合到参考电压线，并且控制端口布置成电容耦合到晶闸管以控制其中的电流流动。在另一实施方案中，晶闸管形成在绝缘体上硅（SOI）结构的掩埋绝缘体层上。利用这些方法，可以严格控制晶闸管中的电流，例如用于数据存储在其中。

6. 发明授权

US06911680B1 Self-aligned thin capacitively-coupled thyristor structure 失效
标题翻译：自对准薄电容耦合晶闸管结构
公开(公告)号：US06911680B1
公开(公告)日：2005-06-28
申请号：US10890031
申请日：2004-07-13
申请人： Andrew Horch , Scott Robins , Farid Nemati
发明人： Andrew Horch , Scott Robins , Farid Nemati
IPC分类号： H01L21/331 , H01L27/11 , H01L29/74 , H01L29/745
CPC分类号： H01L29/66242 , H01L27/11 , H01L29/7436 , H01L29/7455
摘要： A semiconductor memory device having a thyristor is manufactured in a manner that makes possible self-alignment of one or more portions of the thyristor. According to an example embodiment of the present invention, a gate is formed over a first portion of doped substrate. The gate is used to mask a portion of the doped substrate and a second portion of the substrate is doped before or after a spacer is formed. After the second portion of the substrate is doped, the spacer is then formed adjacent to the gate and used to mask the second portion of the substrate while a third portion of the substrate is doped. The gate and spacer are thus used to form self-aligned doped portions of the substrate, wherein the first and second portions form base regions and the third portion form an emitter region of a thyristor. In another implementation, the spacer is also adapted to prevent formation of salicide on the portion of the thyristor beneath the spacer, self-aligning the salicide to the junction between the second and third portions. In addition, dimensions such as width and other characteristics of the doped portions that are used to form a thyristor can be controlled without necessarily using a separate mask.
摘要翻译：制造具有晶闸管的半导体存储器件以能够使晶闸管的一个或多个部分自对准的方式。根据本发明的示例性实施例，在掺杂衬底的第一部分上形成栅极。栅极用于掩模掺杂衬底的一部分，并且衬底的第二部分在形成间隔物之前或之后被掺杂。在衬底的第二部分被掺杂之后，然后在衬底的第三部分被掺杂的同时，将衬底形成为邻近栅极并用于掩蔽衬底的第二部分。因此，栅极和间隔物用于形成衬底的自对准掺杂部分，其中第一和第二部分形成基极区，第三部分形成晶闸管的发射极区。在另一实施方案中，间隔物还适于防止在间隔物下方的可控硅部分上形成自对准硅化物，使自对准硅化物与第二和第三部分之间的连接处。此外，可以控制用于形成晶闸管的掺杂部分的宽度和其它特性的尺寸，而不必使用单独的掩模。

7. 发明授权

US06888177B1 Increased base-emitter capacitance 失效
标题翻译：增加基极 - 发射极电容
公开(公告)号：US06888177B1
公开(公告)日：2005-05-03
申请号：US10253350
申请日：2002-09-24
申请人： Farid Nemati , Scott Robins , Andrew Horch
发明人： Farid Nemati , Scott Robins , Andrew Horch
IPC分类号： H01L21/332 , H01L21/84 , H01L27/108 , H01L27/12 , H01L29/417 , H01L29/74
CPC分类号： H01L27/108 , H01L21/84 , H01L23/535 , H01L27/1203 , H01L29/41716 , H01L29/66393 , H01L2924/0002 , H01L2924/00
摘要： A thyristor-based semiconductor device exhibits a relatively increased base-emitter capacitance. According to an example embodiment of the present invention, the junction area between a base region and an adjacent emitter region of a thyristor is increased, relative to the junction area between other regions in the thyristor. In one implementation, the base region is formed extending on two sides of the emitter region. In another implementation, the thyristor is formed on a buried insulator layer of a silicon-on-insulator (SOI) structure, with the base region having a first portion laterally adjacent to the emitter region and having a second portion between the emitter region and the buried insulator.
摘要翻译：基于晶闸管的半导体器件表现出相对增加的基极 - 发射极电容。根据本发明的示例性实施例，晶闸管的基极区域和相邻发射极区域之间的结面积相对于晶闸管中的其它区域之间的接合面积增加。在一个实施方式中，形成在发射极区域的两侧上延伸的基极区域。在另一种实施方式中，晶闸管形成在绝缘体上硅（SOI）结构的掩埋绝缘体层上，其中基极区域具有与发射极区域相邻的第一部分，并且在发射极区域和发射极区域之间具有第二部分埋绝缘体。

8. 发明授权

US06777271B1 Thyristor-based device including trench isolation 失效
标题翻译：基于晶闸管的器件包括沟槽隔离
公开(公告)号：US06777271B1
公开(公告)日：2004-08-17
申请号：US10201654
申请日：2002-07-23
申请人： Scott Robins , Andrew Horch , Farid Nemati , Hyun-Jin Cho
发明人： Scott Robins , Andrew Horch , Farid Nemati , Hyun-Jin Cho
IPC分类号： H01L21332
CPC分类号： H01L29/66363 , H01L21/76229 , H01L21/76237 , H01L21/763 , H01L27/0617 , H01L27/0817
摘要： A semiconductor device includes a thyristor designed to reduce or eliminate manufacturing and operational difficulties commonly experienced in the formation and operation of NDR devices. According to one example embodiment of the present invention, the semiconductor substrate is trenched adjacent a doped or dopable substrate region, which is formed to included at least two vertically-adjacent thyristor regions of different polarity. A capacitively-coupled control port for the thyristor is coupled to at least one of the thyristor regions. The trench also includes a dielectric material for electrically insulating the vertically-adjacent thyristor regions. The thyristor is electrically connected to other circuitry in the device, such as a transistor, and used to form a device, such as a memory cell.
摘要翻译：半导体器件包括设计用于减少或消除在NDR器件的形成和操作中通常经历的制造和操作困难的晶闸管。根据本发明的一个示例实施例，半导体衬底在掺杂或可掺杂的衬底区域附近被沟槽，该衬底区域形成为包括不同极性的至少两个垂直相邻的晶闸管区域。用于晶闸管的电容耦合控制端口耦合到至少一个晶闸管区域。沟槽还包括用于使垂直相邻的晶闸管区域电绝缘的电介质材料。晶闸管电连接到器件中的其它电路，例如晶体管，并用于形成诸如存储器单元的器件。

9. 发明授权

US07320895B1 Thyristor-based device having dual control ports 失效
标题翻译：具有双控制端口的基于晶闸管的装置
公开(公告)号：US07320895B1
公开(公告)日：2008-01-22
申请号：US11086113
申请日：2005-03-22
申请人： Andrew Horch , Scott Robins , Farid Nemati
发明人： Andrew Horch , Scott Robins , Farid Nemati
IPC分类号： H01L21/00 , H01L21/332
CPC分类号： G11C11/39 , H01L27/1025 , H01L27/1027 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L29/7436
摘要： Switching operations, such as those used in memory devices, are enhanced using a thyristor-based semiconductor device adapted to switch between a blocking state and a conducting state. According to an example embodiment of the present invention, a thyristor-based semiconductor device includes a thyristor having first and second base regions coupled between first and second emitter regions, respectively. A first control port capacitively couples a first signal to the first base region, and a second control port capacitively couples a second signal to the second base region. Each of the first and second signals have a charge that is opposite in polarity, and the opposite polarity signals effect the switching of the thyristor at a lower power, relative to the power that would be required to switch the thyristor having only one control port. In this manner, power consumption for a switching operation can be reduced, which is useful, for example, to correspond with reduced power supplied to other devices in a semiconductor device employing the thyristor.
摘要翻译：使用适于在阻塞状态和导通状态之间切换的基于晶闸管的半导体器件来增强诸如存储器件中使用的切换操作。根据本发明的示例性实施例，基于晶闸管的半导体器件包括分别具有耦合在第一和第二发射极区之间的第一和第二基极区域的晶闸管。第一控制端口将第一信号电容耦合到第一基区，并且第二控制端口将第二信号电容耦合到第二基区。第一和第二信号中的每一个具有极性相反的电荷，相反的极性信号相对于仅具有一个控制端口的晶闸管所需的功率，以较低的功率影响晶闸管的开关。以这种方式，可以减少用于开关操作的功耗，这对于例如提供给采用晶闸管的半导体器件中的其它器件的降低的功率是有用的。

10. 发明授权

US07125753B1 Self-aligned thin capacitively-coupled thyristor structure 失效
标题翻译：自对准薄电容耦合晶闸管结构
公开(公告)号：US07125753B1
公开(公告)日：2006-10-24
申请号：US11159738
申请日：2005-06-23
申请人： Andrew Horch , Scott Robins , Farid Nemati
发明人： Andrew Horch , Scott Robins , Farid Nemati
IPC分类号： H01L21/332
CPC分类号： H01L29/7436 , H01L29/66393
摘要： A semiconductor memory device having a thyristor is manufactured in a manner that makes possible self-alignment of one or more portions of the thyristor. According to an example embodiment of the present invention, a gate is formed over a first portion of doped substrate. The gate is used to mask a portion of the doped substrate and a second portion of the substrate is doped before or after a spacer is formed. After the second portion of the substrate is doped, the spacer is then formed adjacent to the gate and used to mask the second portion of the substrate while a third portion of the substrate is doped. The gate and spacer are thus used to form self-aligned doped portions of the substrate, wherein the first and second portions form base regions and the third portion form an emitter region of a thyristor. In another implementation, the spacer is also adapted to prevent formation of salicide on the portion of the thyristor beneath the spacer, self-aligning the salicide to the junction between the second and third portions. In addition, dimensions such as width and other characteristics of the doped portions that are used to form a thyristor can be controlled without necessarily using a separate mask.
摘要翻译：制造具有晶闸管的半导体存储器件以能够使晶闸管的一个或多个部分自对准的方式。根据本发明的示例性实施例，在掺杂衬底的第一部分上形成栅极。栅极用于掩模掺杂衬底的一部分，并且衬底的第二部分在形成间隔物之前或之后被掺杂。在衬底的第二部分被掺杂之后，然后在衬底的第三部分被掺杂的同时，将衬底形成为邻近栅极并用于掩蔽衬底的第二部分。因此，栅极和间隔物用于形成衬底的自对准掺杂部分，其中第一和第二部分形成基极区域，第三部分形成晶闸管的发射极区域。在另一实施方案中，间隔物还适于防止在间隔物下方的可控硅部分上形成自对准硅化物，使自对准硅化物与第二和第三部分之间的连接处。此外，可以控制用于形成晶闸管的掺杂部分的宽度和其它特性的尺寸，而不必使用单独的掩模。

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