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1. 发明申请

US20220114103A1 GRAPH MEMORY ENGINE 有权
公开(公告)号：US20220114103A1
公开(公告)日：2022-04-14
申请号：US17378647
申请日：2021-07-16
申请人： MoSys, Inc.
发明人： Michael J. Miller
IPC分类号： G06F12/0875
摘要： A system, method, and apparatus for graph memory. In one embodiment, the method includes: traversing program instructions disposed in an associative memory for operating a computer, the method comprising: receiving input data to be processed; identifying a next instruction to be fetched in the memory for processing the input data via: receiving a current node ID of a current state; performing a computational test on the input data resulting in a computed value; generating a search key by combining at least a portion of the computed edge value with the current node ID; and accessing the next instruction in associative memory via the search key.

2. 发明授权

US10114558B2 Integrated main memory and coprocessor with low latency 有权
公开(公告)号：US10114558B2
公开(公告)日：2018-10-30
申请号：US15898659
申请日：2018-02-18
申请人： MoSys, Inc.
发明人： Michael J. Miller , Jay B Patel , Michael J Morrison
IPC分类号： G06F3/06 , G06F9/38 , G06F12/00 , H04L29/12 , H04L29/08 , G06F12/0875 , G06F12/0895
摘要： System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission. Paired I/O ports tied to unique global on-chip SD allow multiple external processors to slave chip and its resources independently and autonomously without scheduling between the external processors.

3. 发明申请

US20150244381A9 DELAY-LOCKED LOOP WITH DUAL LOOP FILTERS FOR FAST RESPONSE AND WIDE FREQUENCY AND DELAY RANGE 审中-公开
标题翻译：具有双循环滤波器的延迟环路用于快速响应和宽频率和延迟范围
公开(公告)号：US20150244381A9
公开(公告)日：2015-08-27
申请号：US14231730
申请日：2014-03-31
申请人： MoSys, Inc.
发明人： Prashant Choudhary , Aldo Bottelli , Charles W. Boecker
IPC分类号： H03L7/07
CPC分类号： H03L1/00 , H03L7/07 , H03L7/08 , H03L7/0816 , H04L7/0338
摘要： A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.
摘要翻译：延迟锁定环路包括用于控制延迟锁定环路中的延迟元件的两个反馈回路。第一反馈回路包括反馈电路，用于基于延迟锁定环路的输入时钟信号与由延迟锁定环路产生的输出时钟信号之间的相位差产生指示延迟调整的反馈信号。第二反馈回路包括功率调节器，其通过使用反馈信号作为参考来调节电源来产生调节信号。延迟锁定环路还包括包括电阻 - 电容网络的可变延迟电路。可变延迟电路基于反馈信号控制电阻 - 电容网络中的电容，并根据调节信号控制电阻 - 电容网络的电阻。以这种方式，可变延迟电路通过基于反馈信号和调节信号两者延迟输入时钟信号来产生输出时钟信号。

4. 发明授权

US09037928B2 Memory device with background built-in self-testing and background built-in self-repair 有权
标题翻译：内存设备背景内置自检和背景内置自修复
公开(公告)号：US09037928B2
公开(公告)日：2015-05-19
申请号：US13732783
申请日：2013-01-02
申请人： Bendik Kleveland , Dipak K Sikdar , Rajesh Chopra , Jay Patel
发明人： Bendik Kleveland , Dipak K Sikdar , Rajesh Chopra , Jay Patel
IPC分类号： G06F11/20 , G11C29/44 , G11C29/16 , G06F11/10 , G11C29/12 , G11C29/06 , G11C29/04
CPC分类号： G06F11/2094 , G06F11/106 , G11C29/06 , G11C29/12 , G11C29/16 , G11C29/42 , G11C29/44 , G11C29/4401 , G11C29/50 , G11C29/808 , G11C2029/0409
摘要： A memory device with background built-in self-testing (BBIST) includes a plurality of memory blocks; a memory buffer to offload data from one of the plurality of memory blocks temporarily; and a memory block stress controller to control a stress test applied to the one of the memory blocks when the data is temporarily offloaded on the memory buffer. The stress test tests for errors in the one of the plurality of the memory blocks.
摘要翻译：具有背景内置自检（BBIST）的存储器件包括多个存储器块; 一个用于临时从多个存储块中的一个存储器块中的一个卸载数据的存储器缓冲器; 以及存储器块应力控制器，用于当数据被暂时地卸载到存储器缓冲器上时，控制施加到存储器块之一的压力测试。压力测试测试多个存储器块中的一个存储器块中的错误。

5. 发明授权

US09030894B2 Hierarchical multi-bank multi-port memory organization 有权
标题翻译：分层多行多端口内存组织
公开(公告)号：US09030894B2
公开(公告)日：2015-05-12
申请号：US13972798
申请日：2013-08-21
申请人： MoSys, Inc.
发明人： Richard S. Roy , Dipak Kumar Sikdar
IPC分类号： G11C7/00 , G11C11/413 , G11C7/10
CPC分类号： G11C7/00 , G11C7/1075 , G11C11/413
摘要： A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory bank performs an access to an array of single-port memory cells. Simultaneous accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead.
摘要翻译：存储器系统包括多个（N）个存储体和多个（M）端口，其中N大于或等于M.存储器组中的每一个耦合到每个端口。在每个端口上同时发送访问请求。然而，每个同时访问请求指定了不同的存储体。每个存储器监视端口上的访问请求，并确定任何访问请求是否指定存储体。在确定访问请求指定存储体时，存储体执行对单端口存储单元阵列的访问。在多个存储体中执行同时访问，提供等于一个存储体的带宽乘以端口数的带宽。可以提供额外的层次级别，这允许以最小的面积开销进一步增加同时访问的端口的数量。

6. 发明授权

US08836381B2 Pseudo-supply hybrid driver 有权
标题翻译：伪供应混合驱动
公开(公告)号：US08836381B2
公开(公告)日：2014-09-16
申请号：US13787692
申请日：2013-03-06
申请人： MoSys, Inc.
发明人： Charles W. Boecker , Eric Groen
IPC分类号： H03B1/00 , H03K17/16
CPC分类号： H03K17/165 , H03K19/018585
摘要： A hybrid output driver includes a voltage mode main driver having an adjustable differential output voltage swing, and a current mode emphasis driver. Differential output voltage swing is adjusted by controlling the resistance of a first adjustable resistor coupled to a first voltage supply terminal, and the resistance of a second adjustable resistor coupled to a second voltage supply terminal. Resistances of the first and second adjustable resistors are adjusted by modifying a number of resistors connected in parallel. A calibration process measures the actual resistance of a similar resistor, and uses this resistance measurement to determine the number of resistors to be connected in parallel to provide the desired resistance. The current mode emphasis driver sources/sinks currents to/from differential output terminals of the hybrid output driver in response to an emphasis signal. These currents are selected in view of the selected differential output voltage swing and selected emphasis level.
摘要翻译：混合输出驱动器包括具有可调差分输出电压摆幅的电压模式主驱动器和当前模式强调驱动器。通过控制耦合到第一电压源端子的第一可调电阻器的电阻和耦合到第二电压端子的第二可调电阻器的电阻来调节差分输出电压摆幅。第一和第二可调电阻器的电阻通过修改并联的多个电阻器来调节。校准过程测量类似电阻器的实际电阻，并使用该电阻测量来确定要并联的电阻器数量，以提供所需的电阻。当前模式强调驱动器响应于加重信号来源/混合混合输出驱动器的差分输出端的电流/来电。考虑到选定的差分输出电压摆幅和选定的强调级别来选择这些电流。

7. 发明授权

US08526265B2 Three state word line driver for a DRAM memory device 有权
标题翻译：用于DRAM存储器件的三态字线驱动器
公开(公告)号：US08526265B2
公开(公告)日：2013-09-03
申请号：US12645321
申请日：2009-12-22
申请人： Jae Kwang Sim
发明人： Jae Kwang Sim
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C11/4085
摘要： A memory bank includes an array of memory cells, word lines for accessing the memory cells, and word line drivers coupled to the word lines. When the memory bank is being accessed, the word line drivers are coupled to receive a first supply voltage, which is applied to the non-selected word lines of the memory bank. The first supply voltage turns off access transistors of the memory cells coupled to the non-selected word lines. When the memory bank is not being accessed, the word line drivers are coupled to receive a second supply voltage, which is applied to each of the word lines of the memory bank. The second supply voltage turns off the access transistors of the memory cells coupled of the word lines. The first and second supply voltages are selected such that the first supply voltage turns off the access transistors harder than the second supply voltage.
摘要翻译：存储体包括存储单元阵列，用于访问存储单元的字线以及耦合到字线的字线驱动器。当存储体被访问时，字线驱动器被耦合以接收施加到存储体的未被选择的字线的第一电源电压。第一电源电压关闭与非选择字线耦合的存储单元的存取晶体管。当存储体未被访问时，字线驱动器被耦合以接收施加到存储体的每个字线的第二电源电压。第二电源电压关闭与字线耦合的存储单元的存取晶体管。选择第一和第二电源电压使得第一电源电压使得存取晶体管比第二电源电压更硬。

8. 发明申请

US20130076450A1 LOW NOISE BIAS CIRCUIT FOR A PLL OSCILLATOR 审中-公开
标题翻译：用于PLL振荡器的低噪声偏置电路
公开(公告)号：US20130076450A1
公开(公告)日：2013-03-28
申请号：US13244254
申请日：2011-09-23
申请人： Chethan Rao , Shaishav Desai , Alvin Wang
发明人： Chethan Rao , Shaishav Desai , Alvin Wang
IPC分类号： H03L7/08
CPC分类号： H03L7/183 , H03L7/0896 , H03L7/0898 , H03L7/093 , H03L7/099 , H03L7/104 , H03L2207/06
摘要： A system, method, and apparatus for generating a low noise bias current to improve jitter performance in a wide frequency range LC-based phase-locked loop (PLL) circuit for multi-speed clocking applications. A plurality of noise-reducing stages are coupled in series and disposed between a power supply and a voltage controlled oscillator (VCO) including: a first stage VCO regulator; and a second stage bias circuit having a plurality of PMOS transistors cascode-coupled to each other and optionally grouped into one or more parallel branches of cascode-coupled transistor pairs. Each branch can be automatically enabled by a calibration code based on the desired reference clock signal in order to provide a wide range of currents to the voltage controlled oscillator. The cascode coupled pair includes a bias transistor coupled in series with a self-biased current buffer to provide high output impedance with minimal current change for any input voltage change from noise.
摘要翻译：一种用于产生低噪声偏置电流以提高用于多速时钟应用的宽频率范围LC基锁相环（PLL）电路中的抖动性能的系统，方法和装置。多个降噪级串联耦合并设置在电源和压控振荡器（VCO）之间，包括：第一级VCO调节器; 以及第二级偏置电路，其具有彼此串联耦合并可选地分组成共源共栅晶体管对的一个或多个并联支路的多个PMOS晶体管。可以通过基于所需参考时钟信号的校准码来自动启用每个分支，以便向压控振荡器提供宽范围的电流。共源共栅耦合对包括与自偏置电流缓冲器串联耦合的偏置晶体管，以便为噪声的任何输入电压变化提供最小电流变化的高输出阻抗。

9. 发明授权

US08368217B2 Integrated circuit package with segregated Tx and Rx data channels 有权
标题翻译：集成电路封装，具有隔离的Tx和Rx数据通道
公开(公告)号：US08368217B2
公开(公告)日：2013-02-05
申请号：US13541658
申请日：2012-07-03
申请人： Michael J. Miller , Mark William Baumann , Richard S. Roy
发明人： Michael J. Miller , Mark William Baumann , Richard S. Roy
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively.
摘要翻译：芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。 Tx端子彼此连续分组，并且作为组分离到包装的给定边缘，Rx端子被类似地分组并分离到包装的不同边缘。 Tx和Rx数据通道设置在封装的相应单层中，或者两者都被布置在封装的相同的单层中。 Rx端口和Tx端口位于封装的大致中心处，Tx和Rx端口设置在平分封装的轴的相应相对两侧。分别从包装的第一边缘到包装的中心以及从包装的中心到包装的第二边缘的相同方向从芯片流接收和传输的数据信号。

10. 发明申请

US20120267769A1 INTEGRATED CIRCUIT PACKAGE WITH SEGREGATED TX AND RX DATA CHANNELS 有权
标题翻译：集成电路封装与分离的TX和RX数据通道
公开(公告)号：US20120267769A1
公开(公告)日：2012-10-25
申请号：US13541658
申请日：2012-07-03
申请人： Michael J. Miller , Mark Baumann , Richard S. Roy
发明人： Michael J. Miller , Mark Baumann , Richard S. Roy
IPC分类号： H01L23/58
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively.
摘要翻译：芯片布局将Rx端子和Rx端口与Tx端子和Tx端口隔离。 Tx端子彼此连续分组，并且作为组分离到包装的给定边缘，Rx端子被类似地分组并分离到包装的不同边缘。 Tx和Rx数据通道设置在封装的相应单层中，或者两者都被布置在封装的相同的单层中。 Rx端口和Tx端口位于封装的大致中心处，Tx和Rx端口设置在平分封装的轴的相应相对两侧。分别从包装的第一边缘到包装的中心以及从包装的中心到包装的第二边缘的相同方向从芯片流接收和传输的数据信号。

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