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1. 发明授权

US09823279B2 Current sensing using a metal-on-passivation layer on an integrated circuit die 有权
公开(公告)号：US09823279B2
公开(公告)日：2017-11-21
申请号：US14818022
申请日：2015-08-04
申请人： Micrel, Inc.
发明人： Cameron Jackson
IPC分类号： G01R19/00 , H01L49/02 , G01R1/20 , H01L23/495 , H01L23/00 , G01R31/28 , H01L23/31
CPC分类号： G01R19/0092 , G01R1/203 , G01R31/2884 , H01L23/3171 , H01L23/49541 , H01L24/17 , H01L28/20 , H01L2224/0401 , H01L2224/05567 , H01L2224/13022 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/1412 , H01L2224/16227 , H01L2224/16245 , H01L2924/19103 , H01L2924/19104 , H01L2924/014
摘要： A current sense resistor integrated with an integrated circuit die where the integrated circuit die is housed in a flip-chip semiconductor package includes a metal layer formed over a passivation layer of the integrated circuit die where the metal layer having an array of metal pillars extending therefrom. The metal pillars are electrically connected to a first leadframe portion and a second leadframe portion of the semiconductor package where the first leadframe portion and the second leadframe portion are electrically isolated from each other and physically separated by a separation of a first distance. The current sense resistor is formed in a portion of the metal layer spanning the separation between the first and second leadframe portions, the first and second leadframe portions forming terminals of the current sense resistor.

2. 发明授权

US09455626B2 Hysteretic buck DC-DC converter 有权
标题翻译：迟滞降压型DC-DC转换器
公开(公告)号：US09455626B2
公开(公告)日：2016-09-27
申请号：US14205025
申请日：2014-03-11
申请人： Micrel, Inc.
发明人： Dashun Xue , William MacLean
IPC分类号： H02M3/158 , H02M3/156 , H02M1/00
CPC分类号： H02M3/156 , H02M3/158 , H02M2001/0025 , H02M2001/007
摘要： A buck switching regulator includes a feedback control circuit using a four-input comparator to regulate the output voltage to a substantially constant level with reduced voltage offset and with fast transient response. In some embodiments, the buck switching regulator uses the four-input comparator to compare a first feedback signal without ripple and a second feedback signal with injected ripple components to a reference level. The four-input comparator generates an output signal to control the switching of the power switches. The buck switching regulator generates an output voltage with increased accuracy and fast transient response. Furthermore, the buck switching regulator can be used with output capacitor having any value of ESR.
摘要翻译：降压开关调节器包括使用四输入比较器的反馈控制电路，以将输出电压调节到具有降低的电压偏移和快速瞬态响应的基本上恒定的电平。在一些实施例中，降压开关调节器使用四输入比较器来将没有波纹的第一反馈信号和具有注入的波纹分量的第二反馈信号与参考电平进行比较。四输入比较器产生一个输出信号来控制电源开关的切换。降压开关调节器以更高的精度和快速的瞬态响应产生输出电压。此外，降压开关稳压器可以与具有任何ESR值的输出电容器一起使用。

3. 发明授权

US09306454B2 Optimal ripple injection for a boost regulator 有权
标题翻译：升压调节器的最佳纹波注入
公开(公告)号：US09306454B2
公开(公告)日：2016-04-05
申请号：US13901407
申请日：2013-05-23
申请人： Micrel, Inc.
发明人： Vinit Jayaraj , Jayant Rao
IPC分类号： G05F1/00 , H02M3/156 , H02M1/15 , H02M3/158 , H02M1/00
CPC分类号： H02M3/1563 , H02M1/15 , H02M3/1588 , H02M2001/0025 , Y02B70/1466
摘要： A boost switching regulator incorporates a ripple injection circuit to generate a voltage ripple signal for feedback control that mimics the actual ripple signal of the regulated output voltage. In this manner, the ripple injection circuit achieves optimal ripple injection for stable and enhanced feedback control. In one embodiment, the injected ripple signal is generated from a current injection signal that mimics the difference between the inductor current that flows through the synchronous rectifier and the load current when the synchronous rectifier is on. The injected voltage ripple signal is generated when the current injection signal is integrated by a feedforward capacitor.
摘要翻译：升压开关稳压器集成了纹波注入电路，以产生用于反馈控制的电压纹波信号，模拟调节输出电压的实际纹波信号。以这种方式，纹波注入电路实现了最佳纹波注入，用于稳定和增强的反馈控制。在一个实施例中，注入的纹波信号是从电流注入信号产生的，电流注入信号模拟同步整流器流过同步整流器的电感电流与当同步整流器导通时的负载电流之间的差值。当电流注入信号由前馈电容器积分时，产生注入电压纹波信号。

4. 发明授权

US09201438B2 Buck DC-DC converter with accuracy enhancement 有权
标题翻译：降压型DC-DC转换器具有精度提高
公开(公告)号：US09201438B2
公开(公告)日：2015-12-01
申请号：US13678322
申请日：2012-11-15
申请人： Micrel, Inc.
发明人： William MacLean , Dashun Xue , Leland Swanson
IPC分类号： G05F1/575 , G05F1/56 , H02M3/156 , G05F1/62 , H02M1/00
CPC分类号： G05F1/62 , H02M1/00 , H02M3/1588 , H02M2001/0025 , H02M2003/1566 , Y02B70/1466
摘要： A buck switching regulator includes a feedback control circuit including a first gain circuit generating a first feedback signal indicative of the regulated output voltage; a ripple generation circuit generating a ripple signal that is injected to the first feedback signal; and a comparator receiving a first reference signal and the first feedback signal to generate a comparator output signal. The switching regulator further includes an offset compensation circuit including a second gain circuit generating a second feedback signal indicative of the regulated output voltage; and an operational transconductance amplifier (OTA) configured to receive the second feedback signal and the first reference signal and to generate an output signal. The output signal of the OTA is coupled to the comparator to adjust an offset to the comparator so as to cancel the offset at the regulated output voltage due to the injected ripple signal.
摘要翻译：降压开关调节器包括反馈控制电路，该反馈控制电路包括产生指示调节输出电压的第一反馈信号的第一增益电路; 纹波产生电路，产生注入到第一反馈信号的纹波信号; 以及比较器，接收第一参考信号和第一反馈信号以产生比较器输出信号。开关调节器还包括偏移补偿电路，其包括产生指示调节输出电压的第二反馈信号的第二增益电路; 以及配置成接收第二反馈信号和第一参考信号并产生输出信号的运算跨导放大器（OTA）。 OTA的输出信号被耦合到比较器以调整比较器的偏移量，以便消除由于注入的纹波信号引起的调节输出电压的偏移。

5. 发明授权

US09094197B2 Adaptive pause time energy efficient ethernet PHY 有权
标题翻译：自适应暂停时间节能以太网PHY
公开(公告)号：US09094197B2
公开(公告)日：2015-07-28
申请号：US14571543
申请日：2014-12-16
申请人： Micrel, Inc.
发明人： Wei-Chieh Chang , Wei-Chi Lo , Charng-Show Li , Menping Chang
IPC分类号： H04L5/16 , H04L12/18
CPC分类号： H04L5/16 , H04L5/1423 , H04L12/12 , H04L12/1881 , Y02D50/40 , Y02D50/42
摘要： An energy efficient Ethernet physical layer (PHY) device including an EEE control module configured to generate a control signal to transition the PHY device into a low power consumption mode based an operating condition, and a pause frame generator module responsive to the control signals to generate a pause frame. The pause frame generator module is configured to send the pause frame to a media access control (MAC) device to reduce an incoming flow of data packets from the MAC device to the PHY device for a pause time duration. In operation, the pause frame generator module generates the pause frame including a pause time indicating the length of time for the PHY device to be in the low power consumption mode. The value of the pause time for each pause frame is determined adaptively based on the type of data traffic to be transmitted from the PHY device.
摘要翻译：一种能量效率以太网物理层（PHY）设备，包括EEE控制模块，其被配置为基于操作条件生成控制信号以将PHY设备转换为低功耗模式;以及暂停帧发生器模块，其响应于所述控制信号而产生一个暂停框架。暂停帧生成器模块被配置为将暂停帧发送到媒体访问控制（MAC）设备，以在暂停时间段内减少从MAC设备到PHY设备的数据分组的传入流。在操作中，暂停帧发生器模块产生暂停帧，其包括指示PHY设备处于低功耗模式的时间长度的暂停时间。基于要从PHY设备发送的数据业务的类型，自适应地确定每个暂停帧的暂停时间的值。

6. 发明授权

US08889518B2 LDMOS transistor with asymmetric spacer as gate 有权
标题翻译： LDMOS晶体管采用非对称间隔器作为栅极
公开(公告)号：US08889518B2
公开(公告)日：2014-11-18
申请号：US13954529
申请日：2013-07-30
申请人： Micrel, Inc.
发明人： Martin Alter , Paul McKay Moore
IPC分类号： H01L21/336 , H01L29/66 , H01L29/423 , H01L29/78 , H01L21/265 , H01L21/266 , H01L21/28 , H01L29/10 , H01L29/06
CPC分类号： H01L29/66681 , H01L21/26586 , H01L21/266 , H01L21/2815 , H01L29/0696 , H01L29/1095 , H01L29/42376 , H01L29/4238 , H01L29/7816
摘要： The present invention provides a laterally diffused metal oxide semiconductor (LDMOS) transistor and a method for fabricating it. The LDMOS transistor includes an n-type epitaxial layer formed on a p-type substrate, and an asymmetric conductive spacer which acts as its gate. The LDMOS transistor also includes a source and a drain region on either side of the asymmetric conductive spacer, and a channel region formed by ion-implantation on the asymmetric conductive spacer. The height of the asymmetric conductive spacer increases from the source region to the drain region. The channel region is essentially completely under the asymmetric conductive spacer and has smaller length than that of the channel region of the prior art LDMOS transistors. The LDMOS transistor of the present invention also includes a field oxide layer surrounding the active region of the transistor, and a thin dielectric layer isolating the asymmetric conductive spacer from the n-type epitaxial layer.
摘要翻译：本发明提供一种横向扩散的金属氧化物半导体（LDMOS）晶体管及其制造方法。 LDMOS晶体管包括形成在p型衬底上的n型外延层和用作其栅极的不对称导电间隔物。 LDMOS晶体管还包括在不对称导电间隔物的两侧上的源极和漏极区域，以及通过离子注入形成在非对称导电间隔物上的沟道区域。不对称导电间隔物的高度从源极区域增加到漏极区域。沟道区基本上完全位于不对称导电间隔物的下面，并且具有比现有技术的LDMOS晶体管的沟道区的长度更短的长度。本发明的LDMOS晶体管还包括围绕晶体管的有源区的场氧化物层和将非对称导电间隔物与n型外延层隔离的薄介电层。

7. 发明授权

US08878287B1 Split slot FET with embedded drain 有权
标题翻译：具有嵌入式漏极的分流槽FET
公开(公告)号：US08878287B1
公开(公告)日：2014-11-04
申请号：US13444884
申请日：2012-04-12
申请人： Paul McKay Moore
发明人： Paul McKay Moore
IPC分类号： H01L29/66
CPC分类号： H01L29/7809 , H01L21/2815 , H01L29/401 , H01L29/41766 , H01L29/41775 , H01L29/42376 , H01L29/66719 , H01L29/66734
摘要： The present invention provides an FET which includes an epitaxial layer and first and second body regions formed over the epitaxial layer. Further, the FET includes a first trench formed in the epitaxial layer between the first and the second body regions. The FET also includes a conductive layer formed on the sidewall of the first trench. The conductive layer acts as gate of the FET. The FET also includes a second trench formed at the bottom of the first trench, a first dielectric layer formed over the conductive layer and on the sidewall of the second trench, and a second dielectric layer formed on the first dielectric layer. Further, the FET includes a conductive layer, which acts as drain, deposited in the first and the second trenches. The FET also includes first and a second source regions formed in the first and second body regions, respectively.
摘要翻译：本发明提供一种FET，其包括外延层和形成在外延层上的第一和第二体区。此外，FET包括形成在第一和第二主体区域之间的外延层中的第一沟槽。 FET还包括形成在第一沟槽的侧壁上的导电层。导电层用作FET的栅极。 FET还包括形成在第一沟槽的底部的第二沟槽，形成在第二沟槽的导电层和侧壁上的第一介电层，以及形成在第一介电层上的第二介电层。此外，FET包括作为漏极的导电层，其沉积在第一沟槽和第二沟槽中。 FET还包括分别形成在第一和第二体区中的第一和第二源极区。

8. 发明授权

US08872556B1 PLL frequency synthesizer with multi-curve VCO implementing closed loop curve searching using charge pump current modulation 有权
标题翻译： PLL频率合成器与多曲线VCO实现闭环曲线搜索使用电荷泵电流调制
公开(公告)号：US08872556B1
公开(公告)日：2014-10-28
申请号：US13874222
申请日：2013-04-30
申请人： Micrel, Inc.
发明人： Juinn-Yan Chen , Wei-Kang Cheng
IPC分类号： H03L7/06 , H03L7/085
CPC分类号： H03L7/103 , H03L5/00 , H03L7/099 , H03L7/1072 , H03L7/1976 , H03L2207/06
摘要： A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a phase and frequency detector driving a charge pump and a digital control circuit configured to generate a curve select signal using a closed loop curve search operation to select one of the operating curves in the multi-curve VCO, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit increases the charge pump current above a nominal current value during the closed loop curve search operation and set the charge pump current to the nominal current value after an operating curve is selected.
摘要翻译：使用具有一组操作曲线的多曲线压控振荡器（VCO）的锁相环电路，每个操作曲线对应于在控制电压范围上的不同频率范围。锁相环电路包括驱动电荷泵的相位和频率检测器和配置成使用闭环曲线搜索操作产生曲线选择信号的数字控制电路，以选择多曲线VCO中的一个操作曲线，所选择的操作曲线被VCO使用以产生输出频率等于或接近锁相环的目标频率的输出信号。在一个实施例中，在闭环曲线搜索操作期间，数字控制电路将电荷泵电流增加到额定电流值以上，并且在选择操作曲线之后将电荷泵电流设置为标称电流值。

9. 发明授权

US08773084B2 Buck-boost converter using timers for mode transition control 有权
标题翻译：降压 - 升压转换器使用定时器进行模式转换控制
公开(公告)号：US08773084B2
公开(公告)日：2014-07-08
申请号：US13277559
申请日：2011-10-20
申请人： Charles A. Casey , David Dearn
发明人： Charles A. Casey , David Dearn
IPC分类号： G05F1/24 , G05F3/16
CPC分类号： H02M3/1582
摘要： A DC-to-DC, buck-boost voltage converter includes a duty cycle controller configured to generate control signals for a buck driver configured to drive first and second buck switching transistors at a buck duty cycle and to generate control signals for a boost driver configured to drive first and second boost switching transistors at a boost duty cycle. The duty cycle controller includes at least a duty cycle timer and an offset timer where the duty cycle controller applies the duty cycle timer and the offset timer to control transitions between the buck, the buck-boost and the boost operation modes of the voltage converter.
摘要翻译： DC-DC降压升压电压转换器包括占空比控制器，其被配置为产生用于降压驱动器的控制信号，所述降压驱动器被配置为以降压占空比驱动第一和第二降压开关晶体管，并且为配置的升压驱动器生成控制信号以升压占空比驱动第一和第二升压开关晶体管。占空比控制器至少包括占空比定时器和偏移定时器，其中占空比控制器施加占空比定时器和偏移定时器来控制电压转换器的降压，降压 - 升压和升压操作模式之间的转换。

10. 发明授权

US08705608B2 Noise discriminator for enhanced noise detection in a passive optical network burst mode receiver 有权
标题翻译：用于无源光网络突发模式接收机中增强噪声检测的噪声识别器
公开(公告)号：US08705608B2
公开(公告)日：2014-04-22
申请号：US13587662
申请日：2012-08-16
申请人： George W. Brown , Thomas S. Wong , Bernd Neumann
发明人： George W. Brown , Thomas S. Wong , Bernd Neumann
IPC分类号： H03K5/19 , H03K7/00
CPC分类号： H03K5/19 , H03K5/1252 , H03K7/00 , H04B10/695
摘要： A noise discriminator circuit and a noise discrimination method in a burst mode receiver is configured to determine the validity of an incoming burst signal by analyzing the timing of the signal edges of incoming signal to look for a time duration conforming to the preamble data bits of a valid burst signal. In one embodiment, the noise discriminator circuit and method analyze the time duration between signal edges of the same pulse of an incoming signal. In another embodiment, the noise discriminator circuit and method analyze the time duration between a first set of pulses of an incoming signal and the time duration between signal edges of a second set of pulses of the incoming signal. When the time durations are within a given time range relating to a predetermined timing separation of a valid burst signal, the incoming signal is validated as a valid burst signal.
摘要翻译：突发模式接收机中的噪声鉴别器电路和噪声识别方法被配置为通过分析输入信号的信号边沿的定时来确定输入突发信号的有效性，以寻找符合一个有效突发信号。在一个实施例中，噪声识别器电路和方法分析输入信号的相同脉冲的信号边沿之间的持续时间。在另一个实施例中，噪声鉴别器电路和方法分析入射信号的第一组脉冲与输入信号的第二组脉冲的信号沿之间的持续时间之间的持续时间。当持续时间在与有效突发信号的预定时间间隔相关的给定时间范围内时，输入信号被验证为有效的突发信号。

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