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1. 发明授权

US08861584B2 Noise discriminator for passive optical network burst mode receiver 有权
标题翻译：无源光网络突发模式接收机的噪声识别器
公开(公告)号：US08861584B2
公开(公告)日：2014-10-14
申请号：US13587639
申请日：2012-08-16
申请人： George W. Brown , Thomas S. Wong , Bernd Neumann
发明人： George W. Brown , Thomas S. Wong , Bernd Neumann
IPC分类号： H03K7/04 , H03K7/06 , H03K9/04 , H03K9/06 , H03K7/00 , H03K5/19
CPC分类号： H03K5/19 , H03K5/1252 , H03K7/00 , H04B10/695
摘要： A noise discriminator circuit and a noise discrimination method in a burst mode receiver is configured to determine the validity of an incoming burst signal by analyzing the timing of the signal edges of incoming signal to look for a time duration conforming to the preamble data bits of a valid burst signal. In one embodiment, the noise discriminator circuit and method analyze the time duration between signal edges of the same pulse of an incoming signal. In another embodiment, the noise discriminator circuit and method analyze the time duration between a first set of pulses of an incoming signal and the time duration between signal edges of a second set of pulses of the incoming signal. When the time durations are within a given time range relating to a predetermined timing separation of a valid burst signal, the incoming signal is validated as a valid burst signal.
摘要翻译：突发模式接收机中的噪声鉴别器电路和噪声识别方法被配置为通过分析输入信号的信号边沿的定时来确定输入突发信号的有效性，以寻找符合一个有效突发信号。在一个实施例中，噪声识别器电路和方法分析输入信号的相同脉冲的信号边沿之间的持续时间。在另一个实施例中，噪声鉴别器电路和方法分析入射信号的第一组脉冲与输入信号的第二组脉冲的信号沿之间的持续时间之间的持续时间。当持续时间在与有效突发信号的预定时间间隔相关的给定时间范围内时，输入信号被验证为有效的突发信号。

2. 发明申请

US20130279903A1 Noise Discriminator for Enhanced Noise Detection In A Passive Optical Network Burst Mode Receiver 有权
标题翻译：无源光网络突发模式接收机中增强噪声检测的噪声鉴别器
公开(公告)号：US20130279903A1
公开(公告)日：2013-10-24
申请号：US13587662
申请日：2012-08-16
申请人： George W. Brown , Thomas S. Wong , Bernd Neumann
发明人： George W. Brown , Thomas S. Wong , Bernd Neumann
IPC分类号： H04B10/06 , H03K5/19 , H04B17/00
CPC分类号： H03K5/19 , H03K5/1252 , H03K7/00 , H04B10/695
摘要： A noise discriminator circuit and a noise discrimination method in a burst mode receiver is configured to determine the validity of an incoming burst signal by analyzing the timing of the signal edges of incoming signal to look for a time duration conforming to the preamble data bits of a valid burst signal. In one embodiment, the noise discriminator circuit and method analyze the time duration between signal edges of the same pulse of an incoming signal. In another embodiment, the noise discriminator circuit and method analyze the time duration between a first set of pulses of an incoming signal and the time duration between signal edges of a second set of pulses of the incoming signal. When the time durations are within a given time range relating to a predetermined timing separation of a valid burst signal, the incoming signal is validated as a valid burst signal.
摘要翻译：突发模式接收机中的噪声鉴别器电路和噪声识别方法被配置为通过分析输入信号的信号边沿的定时来确定输入突发信号的有效性，以寻找符合一个有效突发信号。在一个实施例中，噪声识别器电路和方法分析输入信号的相同脉冲的信号边沿之间的持续时间。在另一个实施例中，噪声鉴别器电路和方法分析入射信号的第一组脉冲与输入信号的第二组脉冲的信号沿之间的持续时间之间的持续时间。当持续时间在与有效突发信号的预定时间间隔相关的给定时间范围内时，输入信号被验证为有效的突发信号。

3. 发明授权

US07408994B1 AC coupling system for wide band digital data with dynamic AC load 有权
标题翻译：交流耦合系统，用于宽带数字数据与动态交流负载
公开(公告)号：US07408994B1
公开(公告)日：2008-08-05
申请号：US10622337
申请日：2003-07-18
申请人： Thomas S. Wong , George W. Brown
发明人： Thomas S. Wong , George W. Brown
IPC分类号： H04B3/00 , H04L25/10 , H03H11/16
CPC分类号： H04L25/0278
摘要： An interface system couples a fixed impedance device to a receiver for transmitting data signals at different data rates at different times. The interface system includes elements that are connected to provide different time constants of responsiveness to data signals of higher and lower data rates without distorting the data signals beyond usability.
摘要翻译：接口系统将固定阻抗装置耦合到接收器，用于在不同时间以不同的数据速率传输数据信号。接口系统包括连接的元件，以提供对具有较高和较低数据速率的数据信号的响应性的不同时间常数，而不会使数据信号超出可用性。

4. 发明授权

US06690940B1 System for selective prevention of non-emergency use of an electronic device 有权
标题翻译：用于选择性地防止非紧急使用电子设备的系统
公开(公告)号：US06690940B1
公开(公告)日：2004-02-10
申请号：US09668099
申请日：2000-09-22
申请人： James W. Brown , George W. Brown , Charles F. Brown
发明人： James W. Brown , George W. Brown , Charles F. Brown
IPC分类号： H04Q720
CPC分类号： H04M1/6075 , H04M1/66 , H04W48/04 , H04W64/00 , H04W64/006 , H04W84/042 , H04W88/02
摘要： A system for selectively disabling use of at least selected features of a stand-alone electronic device under a predetermined set of conditions. The system establishes a state of the set of conditions as being satisfied or unsatisfied, communicates the state to the electronic device, and disables the selected features if the state is satisfied. In one embodiment, the system may be advantageously be used to prevent vehicular accidents by at least partially disabling non-emergency use of a wireless telephone in a moving vehicle. In another embodiment, the system may be used to disable features of an electronic device within a predetermined area having a boundary that is independent of a communications network cell.
摘要翻译：一种用于在预定条件下选择性地禁用独立电子设备的至少所选特征的使用的系统。系统建立满足或不满足条件的状态，将状态传达到电子设备，如果状态满足，则禁用所选择的特征。在一个实施例中，系统可以有利地用于通过至少部分地禁用移动车辆中的无线电话的非紧急使用来防止车辆事故。在另一个实施例中，该系统可以用于禁用具有独立于通信网络小区的边界的预定区域内的电子设备的特征。

5. 发明授权

US4577294A Redundant memory circuit and method of programming and verifying the circuit 失效
标题翻译：冗余内存电路和编程和验证电路的方法
公开(公告)号：US4577294A
公开(公告)日：1986-03-18
申请号：US485695
申请日：1983-04-18
申请人： George W. Brown , Phi Thai
发明人： George W. Brown , Phi Thai
IPC分类号： G11C17/00 , G11C29/00 , G11C29/04 , G11C29/24 , G11C11/40 , G11C7/00
CPC分类号： G11C29/785 , G11C29/24
摘要： A redundant memory circuit having a memory for storing information in a matrix of interconnected rows and columns, and a row and a column address decoder to access the rows and columns. The memory has a redundant row or rows to replace a defective row or rows in the matrix and a programmable decoder which is programmed with the row address of the defective row to access the redundant row. The row and column address decoders are used to access the defective row and to sequentially access the columns so as to entirely disconnect the defective row from the columns. The programmable decoder is then programmed with the defective row address, bit by bit, in response to the column addresses, to access the redundant row. After this procedure, a verification circuit can be used to verify that the redundant row can be accessed and that the programmable decoder is properly programmed to decode only one address to one row.
摘要翻译：一种冗余存储器电路，具有用于存储互连的行和列的矩阵中的信息的存储器，以及用于访问行和列的行和列地址解码器。存储器具有冗余行或行来替换矩阵中的有缺陷的行或行，以及可编程解码器，其被编程为有缺陷行的行地址以访问冗余行。行和列地址解码器用于访问有缺陷的行并且顺序地访问列，以便将缺陷行与列完全断开。然后，可编程解码器响应于列地址逐位地编程有缺陷的行地址，以访问冗余行。在该过程之后，可以使用验证电路来验证冗余行可以被访问，并且可编程解码器被适当地编程以仅将一个地址解码为一行。

6. 发明授权

US4215282A Temperature compensated sense amplifier for PROMs and the like 失效
标题翻译：用于PROM的温度补偿读出放大器等
公开(公告)号：US4215282A
公开(公告)日：1980-07-29
申请号：US930512
申请日：1978-08-03
申请人： George W. Brown , Thomas L. Reynolds
发明人： George W. Brown , Thomas L. Reynolds
IPC分类号： G11C17/18 , H03K5/153
CPC分类号： G11C17/18
摘要： A sense amplifier and sensing scheme for sensing the normal or blown condition of fuses in a programmable read only memory (PROM) or similar device. A sensing circuit is provided with a threshold level separating high and low input levels indicative of the fuse condition. The sensing circuit has one circuit branch with a first current mirror with a temperature characteristic which provides a threshold level which is slightly divergent with reference to a low level input. Another circuit branch clamps the high input level to the slightly divergent threshold level and uses a second current mirror with a temperature characteristic which provides a high level slightly more divergent than the threshold level. By selecting mirror currents proportionally, high level and threshold level temperature characteristic divergence can be proportionally controlled in selected amounts with respect to the low level. Current sources for the sense amplifier are made to offset voltage fluctuations, making the sense amplifier highly insensitive to voltage fluctuations in addition to temperature variations.
摘要翻译：用于感测可编程只读存储器（PROM）或类似装置中的熔丝的正常或熔断状态的读出放大器和感测方案。感测电路具有分离指示保险丝状况的高和低输入电平的阈值电平。感测电路具有一个具有第一电流镜的电路支路，该第一电流镜具有提供相对于低电平输入稍微发散的阈值电平的温度特性。另一个电路支路将高输入电平钳位到稍微发散的阈值电平，并使用带有温度特性的第二电流镜，该温度特性提供比阈值电平略高的发散级别。通过按比例选择反射镜电流，可以按照低电平成比例地控制高电平和阈值电平温度特性发散。读出放大器的电流源用于抵消电压波动，使得除了温度变化之外，读出放大器对电压波动高度不敏感。

7. 发明授权

US4079308A Resistor ratio circuit construction 失效
标题翻译：电阻比电路结构
公开(公告)号：US4079308A
公开(公告)日：1978-03-14
申请号：US763861
申请日：1977-01-31
申请人： George W. Brown
发明人： George W. Brown
IPC分类号： G05F3/30 , H03H11/24 , G05F1/50
CPC分类号： H03H11/24 , G05F3/30 , Y10T29/49004
摘要： A circuit and method for providing a desired resistor ratio whereby an output voltage may be derived across one of the members of the ratio pair. A voltage regulator is connected between first and second resistors of the ratio pair to provide voltage compensation partially dependent on third and fourth resistors within the regulator such that the error in each of the resistances of the desired ratio pair is cancelled by matching errors in the third and fourth resistances of the voltage regulator.
摘要翻译：一种用于提供期望电阻比的电路和方法，由此输出电压可以通过比对对中的一个元件导出。电压调节器连接在比率对的第一和第二电阻器之间，以提供部分依赖于调节器内的第三和第四电阻器的电压补偿，使得期望比率对的每个电阻中的误差通过匹配第三和电压调节器的第四个电阻。

8. 发明授权

US4035784A Asymmetrical memory cell arrangement 失效
标题翻译：不对称存储单元布置
公开(公告)号：US4035784A
公开(公告)日：1977-07-12
申请号：US642956
申请日：1975-12-22
申请人： George W. Brown
发明人： George W. Brown
IPC分类号： G11C14/00 , G11C7/20 , G11C11/411 , G11C17/00 , H01L21/822 , H01L27/04 , H03K3/356 , G11C11/40
CPC分类号： G11C17/00 , G11C11/4116 , G11C7/20 , H03K3/356008
摘要： A memory cell is provided which comprises a word line, a current source line, a pair of bit lines, a first transistor having a base terminal, a collector terminal coupled to the word line, a first emitter coupled to a first of the pair of bit lines, a second emitter coupled to the current source line, a second transistor having a base terminal coupled to the collector terminal of the first transistor, a collector terminal coupled to the word line and to the base of the first transistor, a first emitter coupled to a second of the pair of bit lines, and a second emitter coupled to the current source line, and means for directing more current through the second transistor than through the first transistor.
摘要翻译：提供了一种存储单元，其包括字线，电流源线，一对位线，具有基极端子的第一晶体管，耦合到该字线的集电极端子，耦合到所述一对位线，耦合到电流源极线的第二发射极，具有耦合到第一晶体管的集电极端子的基极端子的第二晶体管，耦合到字线和第一晶体管的基极的集电极端子，第一发射极耦合到一对位线中的第二个，以及耦合到电流源极线的第二发射极，以及用于引导更多电流通过第二晶体管而不是通过第一晶体管的装置。

9. 发明授权

US1046257A Rod-bender. 失效
标题翻译： ROD-BENDER
公开(公告)号：US1046257A
公开(公告)日：1912-12-03
申请号：US1912674600
申请日：1912-01-31
申请人： GEORGE W BROWN
发明人： KENNEDY JOHN J
CPC分类号： B21D5/04 , B21H5/02

10. 发明授权

US4706934A Gate valve 失效
标题翻译：闸阀
公开(公告)号：US4706934A
公开(公告)日：1987-11-17
申请号：US899539
申请日：1986-08-22
申请人： George W. Brown
发明人： George W. Brown
IPC分类号： F16K3/18 , F16K25/00
CPC分类号： F16K3/184
摘要： A gate valve includes a body which includes first and second valve seats. First and second gates are mounted for movement adjacent to the valve seats, and each of the gates has an outer face adapted to seal against the respective valve seat and an inner face which defines a thrust pad. A wedge is interposed between the first and second gates, and the wedge defines first and second converging wedge faces rigidly positioned with respect to one another to bear against the respective thrust pads. At least one of the thrust pads and the wedge faces defines a convex surface. A hand wheel axially moves the wedge with respect to the body and the wedge is coupled to the gates such that movement of the wedge away from the valve seats moves the gates away from the valve seats. The convex surface allows the respective gate to articulate with respect to the wedge as necessary to align with the valve seat. The wedge is coupled to an actuating member shaped to abut the gates, and springs are placed between the wedge and the gates to bias the gates into contact with the actuating member.
摘要翻译：闸阀包括包括第一和第二阀座的主体。第一和第二门被安装用于邻近阀座移动，并且每个门具有适于密封相应阀座的外表面和限定止推垫的内表面。楔形件插入在第一和第二门之间，并且楔形件限定相对于彼此刚性地定位的第一和第二会聚楔形面，以抵靠相应的推力垫。止推垫和楔形面中的至少一个限定凸面。手轮相对于主体轴向地移动楔形物，并且楔形件联接到闸门，使得楔形物远离阀座的运动使门远离阀座移动。凸形表面允许相应的浇口相对于楔形件相互关联，根据需要与阀座对准。楔形件联接到成形为邻接门的致动构件，并且弹簧被放置在楔形件和门之间，以将门偏置成与致动构件接触。

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