专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4212100A Stable N-channel MOS structure 失效
标题翻译：稳定的N沟道MOS结构
公开(公告)号：US4212100A
公开(公告)日：1980-07-15
申请号：US835985
申请日：1977-09-23
申请人： John Paivinen , Walter D. Eisenhower, Jr. , Ernest R. Helfrich
发明人： John Paivinen , Walter D. Eisenhower, Jr. , Ernest R. Helfrich
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8246 , H01L27/112 , H01L29/417 , H01L29/49 , B01J17/00
CPC分类号： H01L29/66621 , H01L29/4925
摘要： An N-channel MOS integrated circuit device having a composite metal gate structure which has improved temperature stability. The gate structure uses a polysilicon layer to separate the conventional metal gate from the conventional underlying gate oxide. The metal gate and the polysilicon layer extend laterally at least to the lateral extent of the gate region. This composite metal gate structure improves the temperature stability of the IC, and may be used, for example, in read-only memory (ROM) applications. The polysilicon layer is formed without additional photolithographic steps.
摘要翻译：具有具有改善的温度稳定性的复合金属栅极结构的N沟道MOS集成电路器件。栅极结构使用多晶硅层将传统的金属栅极与传统的底层栅极氧化物分离。金属栅极和多晶硅层至少横向延伸到栅极区域的横向延伸。该复合金属栅极结构提高了IC的温度稳定性，并且可以用于例如只读存储器（ROM）应用中。形成多晶硅层而没有额外的光刻步骤。

2. 发明授权

US4099232A Interval timer arrangement in a microprocessor system 失效
标题翻译：微处理器系统中的间隔定时器布置
公开(公告)号：US4099232A
公开(公告)日：1978-07-04
申请号：US723208
申请日：1976-09-14
申请人： William D. Mensch, Jr.
发明人： William D. Mensch, Jr.
IPC分类号： G06F9/48 , G06F1/04
CPC分类号： G06F9/4825
摘要： An interval timer in a MOS IC microprocessor system uses a countdown register of as many stages as the data bus lines (8) but effectively doubles the capacity of that register, without increasing the number of data bus lines or repetitive loading, by interposing a prescale divide-down register between the system clock and the countdown register. The prescale register divides the system clock by one of several selectable factors equal to non-contiguous powers of two (e.g., by 1, 8, 64 or 1,024) to establish respective prescale time periods (of 1, 8, 64 or 1024 system clocK pulses). One of the several possible prescaling factors is selected by a pair of lines from the system address bus. As a result, the interval timer can be configured with one load operation for an interval within a range which was possible in the prior art only with double the number of data lines and double the length of the countdown register. Chip layout is thus optimized, and the number of control lines needed to access timer functions is reduced, with acceptable loss of flexibility.
摘要翻译： MOS IC微处理器系统中的间隔定时器使用与数据总线（8）一样多级的倒计数寄存器，但是通过插入预分频器，而不增加数据总线数量或重复加载，有效地使该寄存器的容量增加一倍系统时钟与倒计时寄存器之间的分频寄存器。预分频比寄存器将系统时钟除以等于两个不连续功率（例如，1,8,84或1,024）的几个可选因子之一，以建立各自的预分频时间段（1,8,84或1024系统clocK 脉冲）。几种可能的预分频因子之一是通过系统地址总线中的一条线选择。因此，间隔定时器可以在一个范围内的间隔内配置一个负载操作，这在现有技术中可能只有两倍数据线，并且倒数寄存器的长度是双倍。因此，芯片布局被优化，并且减少了访问定时器功能所需的控制线的数量，具有可接受的灵活性损失。

3. 发明授权

US4074301A Field inversion control for N-channel device integrated circuits 失效
标题翻译： N沟道器件集成电路的场反演控制
公开(公告)号：US4074301A
公开(公告)日：1978-02-14
申请号：US737547
申请日：1976-11-01
申请人： John O. Paivinen , Walter D. Eisenhower
发明人： John O. Paivinen , Walter D. Eisenhower
IPC分类号： H01L21/265 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/78
CPC分类号： H01L27/0883 , H01L21/2652 , H01L21/8234 , H01L29/0638
摘要： The field inversion properties of integrated circuits incorporating N-channel MOS devices are improved by using a silicon substrate whose bulk dopant concentration is low, but whose local dopant concentration is high at the field surfaces under the field oxide separating the active surface areas where the individual N-channel MOS devices are formed. The differential doping between surface areas under the field oxide and the active surface areas of the substrate is done by nonselectively ion-implanting boron into the substrate to form a uniform low resistivity layer, removing selected portions of the low resistivity layer to expose the unimplanted, high resistivity substrate and forming the active devices at the unimplanted substrate portions. As an option, the unimplanted surface portion can be doped to an intermediate dopant concentration to improve performance. The remaining pattern of the low resistivity layer is covered with field oxide. The invention allows the use of relatively inexpensive, low dopant concentration substrates to conveniently manufacture high performance N-channel MOS integrated circuits.

4. 发明授权

US3941989A Reducing power consumption in calculators 失效
标题翻译：降低计算器的功耗
公开(公告)号：US3941989A
公开(公告)日：1976-03-02
申请号：US532596
申请日：1974-12-13
申请人： Donald L. McLaughlin , Ronald W. Streiber
发明人： Donald L. McLaughlin , Ronald W. Streiber
IPC分类号： G06F1/08 , G06F1/32 , G06F7/38 , G06F1/04
CPC分类号： G06F1/3228 , G06F1/08
摘要： Continuous power and a high rate clock are supplied to a calculator while it is in an execute mode and is actually decoding and processing input information, but lower duty cycle power and lower duty cycle clock pulses are supplied during the subsequent display mode, when the only requirement is to maintain and display selected information resulting from the execute cycle, so as to reduce the power consumption rate as compared to the rate during the execute mode. If there is no new execute mode within a selected time interval, the display is turned off and the duty cycle of the power and the clock supplied to the calculator are lowered still further so as to maintain (without displaying) selected stored information but to further reduce the rate of power consumption.
摘要翻译：连续功率和高速率时钟在处于执行模式时被提供给计算器，并且实际上是解码和处理输入信息，但是在随后的显示模式期间提供较低的占空比功率和较低的占空比时钟脉冲要求是维护和显示从执行周期产生的所选择的信息，以便与执行模式期间的速率相比降低功耗率。如果在所选择的时间间隔内没有新的执行模式，则显示被关闭，并且提供给计算器的电源和时钟的占空比进一步降低，以便维持（不显示）选择的存储信息，但是进一步降低功耗。

5. 发明授权

US3829213A Artproof method for semiconductor devices 失效
标题翻译：用于半导体器件的ARTPROOF方法
公开(公告)号：US3829213A
公开(公告)日：1974-08-13
申请号：US25901672
申请日：1972-06-02
申请人： MOS TECHNOLOGY INC
发明人： PAYNE P
IPC分类号： G03F1/90 , G03B27/02
CPC分类号： G03F1/90
摘要： A method of checking the adherence to design rules, circuit configuration requirements and registration in artwork patterns to be used as masks in the fabrication of semiconductor devices, by forming a composite multicolor display of the artwork, before the masks have been made, wherein each pattern except one or more is presented in a unique color and the remaining pattern is represented by the absence of a color. The method includes contact printing a succession of artwork sheets on a base sheet, in registry with each other, each such sheet being printed in a unique color. In order to represent a selected artwork sheet by the absence of a color, a negative film copy is made of that artwork sheet and the copy is registered with another artwork sheet. The combination of the negative film copy and artwork sheet is then printed onto the base sheet in a selected color to form a subtraction image, i.e., only those portions of the artwork sheet which do not coincide with opaque areas on the negative copy are printed on the base sheet. This method of representing an artwork pattern by a missing color is particularly useful where the pattern represented by the missing color occurs, usually or exclusively, within areas of the pattern on another artwork sheet, as for example, where the pattern represented by missing color corresponds to a mask for cutting contact holes in MOS (metal-oxide-silicon) devices.

6. 发明授权

US3708690A Shift register 失效
标题翻译：移位寄存器
公开(公告)号：US3708690A
公开(公告)日：1973-01-02
申请号：US3708690D
申请日：1971-02-22
申请人： MOS TECHNOLOGY INC
发明人： PAIVINEN J
IPC分类号： G06F5/08 , G11C19/18 , G11C19/00
CPC分类号： G06F5/08 , G11C19/184
摘要： A multi-phase shift register having a plurality of parallel columns each comprising n stages, where n is preferably greater than 3, and where the data is advanced along each such column by first shifting the data from its nth stage to the column output terminal, then from the preceding stage to the nth stage, and then from each of the next preceding stages sequentially to their succeeding stages, until the first stage of the column is reached, whereupon the first stage is emptied of data and free to receive new input data. The advance sequence of the parallel columns is synchronized with the application of the input data, and this sequence is constantly repeated, so that successive input bits of data are directed to different respective columns of the shift register, and then along these columns to their common output terminal, where the pulses are recombined to form the original input pulse series. In one embodiment the advance sequence is delayed one clock pulse in each successive column, so that each column delivers an output pulse, and is ready to receive new input data, one clock pulse behind the preceding column. In another embodiment, successive n bits of data are delayed relative to one another and applied simultaneously to different first stages of n parallel columns, and then are advanced along the column simultaneously with the same advance sequence. At the output of the columns, the bits of data are again delayed and recombined to form the original time sequence series. Several of these multi-phase shift registers are generally connected in cascade, and the advance sequences of the cascaded registers synchronized, so that a large number of data bits may be stored and shifted along the respective columns of the register.
摘要翻译：一种具有多个平行列的多相移位寄存器，每个并行列包括n个级，其中n优选地大于3，并且其中通过首先将数据从第n级移位到列输出端，沿着每个这样的列前进数据，然后从前一阶段到第n阶段，然后从下一个前一阶段的每一个顺序到其后续阶段，直到达到列的第一阶段，然后第一阶段被清空数据并且可以自由地接收新的输入数据。并行列的提前顺序与输入数据的应用同步，并且该序列不间断地重复，使得数据的连续输入位被引导到移位寄存器的不同相应的列，然后沿着这些列到它们的公共输出端子，其中脉冲被重新组合以形成原始输入脉冲序列。在一个实施例中，提前序列在每个连续列中延迟一个时钟脉冲，使得每个列传送输出脉冲，并且准备好接收新的输入数据，在前一列之后的一个时钟脉冲。在另一个实施例中，连续的n位数据相对于彼此延迟并同时施加到n个平行列的不同第一级，然后沿同一列以同样的前进序列前进。在列的输出端，数据位再次被延迟并重新组合以形成原始时间序列。这些多相移位寄存器中的几个通常级联连接，并且级联寄存器的提前序列同步，使得可以沿着寄存器的相应列存储和移位大量的数据位。

7. 发明授权

US4081699A Depletion mode coupling device for a memory line driving circuit 失效
标题翻译：用于存储器线路驱动电路的耗尽模式耦合器件
公开(公告)号：US4081699A
公开(公告)日：1978-03-28
申请号：US723207
申请日：1976-09-14
申请人： Ernie R. Hirt , William Mensch, Jr. , Richard M. Greene
发明人： Ernie R. Hirt , William Mensch, Jr. , Richard M. Greene
IPC分类号： G11C11/4076 , G11C11/4094 , H03K5/02 , H03K19/0185 , H03K19/096 , H03K17/60 , H03K3/353 , H03K17/04 , H03K17/12
CPC分类号： G11C11/4076 , G11C11/4094 , H03K19/01855 , H03K19/096 , H03K5/023
摘要： A circuit for energizing a memory drive line depending on the state of a control signal and the states of two complementary clocks uses a depletion mode MOS coupling device rather than the conventional enhancement mode device used in such cases, and energizes the memory line with a higher voltage than possible in the prior art and at better rise and fall times.
摘要翻译：根据控制信号的状态和两个互补时钟的状态对存储器驱动线进行供电的电路使用耗尽型MOS耦合器件，而不是在这种情况下使用的常规增强模式器件，并且以更高的电压为存储器线供电电压高于现有技术中的可能性，并且具有更好的上升和下降时间。

8. 发明授权

US4011105A Field inversion control for N-channel device integrated circuits 失效
标题翻译： N沟道器件集成电路的场反演控制
公开(公告)号：US4011105A
公开(公告)日：1977-03-08
申请号：US613537
申请日：1975-09-15
申请人： John O. Paivinen , Walter D. Eisenhower
发明人： John O. Paivinen , Walter D. Eisenhower
IPC分类号： H01L21/265 , H01L21/8234 , H01L27/088 , H01L29/06
CPC分类号： H01L27/0883 , H01L21/2652 , H01L21/8234 , H01L29/0638
摘要： The field inversion properties of integrated circuits incorporating N-channel MOS devices are improved by using a silicon substrate whose bulk dopant concentration is low, but whose local dopant concentration is high at the field surfaces under the field oxide separating the active surface areas where the individual N-channel MOS devices are formed. The differential doping between surface areas under the field oxide and the active surface areas of the substrate is done by nonselectively ion-implanting boron into the substrate to form a uniform low resistivity layer, removing selected portions of the low resistivity layer to expose the unimplanted, high resistivity substrate and forming the active devices at the unimplanted substrate portions. As an option, the unimplanted surface portion can be doped to an intermediate dopant concentration to improve performance. The remaining pattern of the low resistivity layer is covered with field oxide. The invention allows the use of relatively inexpensive, low dopant concentration substrates to conveniently manufacture high performance N-channel MOS integrated circuits.

9. 发明授权

US3762039A Plastic encapsulation of microcircuits 失效
标题翻译：微胶囊塑料包封
公开(公告)号：US3762039A
公开(公告)日：1973-10-02
申请号：US3762039D
申请日：1971-09-10
申请人： MOS TECHNOLOGY INC
发明人： DOUGLASS R , MC DULIN C
IPC分类号： B29C70/72 , H01L23/04 , H01L23/057 , H01L23/31 , H01L23/495 , B01J17/00
CPC分类号： B29C70/72 , H01L23/041 , H01L23/057 , H01L23/315 , H01L23/49541 , H01L24/48 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2924/00014 , H01L2924/01079 , H01L2924/01322 , H01L2924/09701 , H01L2924/16195 , H01L2924/181 , Y10T29/49121 , H01L2924/00 , H01L2224/45099
摘要： Microcircuits are encapsulated in a hermetic plastic package by enclosing the ends of conductive leads in an open cavity arranged to house the microcircuit and defined by an inner casing, then positioning a microcircuit in the open cavity and electrically connecting the ends of the conductive leads to the microcircuit, thereafter, covering the open cavity and defining a closed cavity about the microcircuit, and then completely encapsulating the inner casing and adjacent portions of the conductive leads with an outer plastic molded casing.
摘要翻译：将微电路封装在密封塑料封装中，将导电引线的端部封闭在开放空腔中，该开放空腔布置成容纳微电路并由内壳限定，然后将微电路定位在开放空腔中并将导电引线的端部电连接到微电路，然后覆盖开放空腔并且围绕微电路限定闭合腔，然后用外部塑料模制外壳完全封装导电引线的内壳和相邻部分。

10. 发明授权

US3737879A Self-refreshing memory 失效
标题翻译：自我修复记忆
公开(公告)号：US3737879A
公开(公告)日：1973-06-05
申请号：US3737879D
申请日：1972-01-05
申请人： MOS TECHNOLOGY INC
发明人： GREENE R , MCLAUGHLIN D , PAIVINEN J
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A self-refresh circuit having a counter connected to each row of a memory matrix. The matrix is formed of memory units which require repeated refreshing to retain the stored information and the maximum count of each counter corresponds in time to the maximum time that the memory units are permitted to be without a refresh. Each time a row of the matrix is accessed for a writing or a reading and restore operation, the corresponding row counter is reset and its count begins again, so that if at any time the row is not accessed within the period permitted for refreshing a memory unit, its counter completes its count and initiates a mandatory refresh operation for that row while temporarily inhibiting all access to the memory. Also, there is a program sensing unit which determines from the nature of the program steps when access to the memory is not required for a sufficiently long time to permit one or more rows of the memory to be refreshed. When such a time period is detected, a voluntary refresh operation of one or more memory rows nearest to requiring a mandatory refresh is effected, and the corresponding row counters are reset to avoid any interference with the mandatory refresh operation and yet minimize the time in which access to the memory will be inhibited for purposes of memory refresh.
摘要翻译：具有连接到存储器矩阵的每一行的计数器的自刷新电路。该矩阵由需要重复刷新以保留所存储的信息的存储器单元形成，并且每个计数器的最大计数在时间上对应于允许存储器单元没有刷新的最大时间。每次访问一行矩阵进行写入或读取和恢复操作时，相应的行计数器将被重置，并且其计数再次开始，因此如果在任何时候在允许刷新存储器的时间段内访问该行单元，其计数器完成其计数，并启动该行的强制刷新操作，同时临时禁止对存储器的所有访问。而且，存在程序感测单元，其从程序步骤的性质确定在不需要足够长的时间的情况下访问存储器以允许刷新存储器的一行或多行。当检测到这样的时间段时，实现一个或多个存储器行的自愿刷新操作，最近需要强制刷新，并且相应的行计数器被重置以避免对强制刷新操作的任何干扰，并且最小化时间存储器的访问将被禁止用于内存刷新。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式