专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4972251A Multilayer glass passivation structure and method for forming the same 失效
标题翻译：多层玻璃钝化结构及其形成方法
公开(公告)号：US4972251A
公开(公告)日：1990-11-20
申请号：US765892
申请日：1985-08-14
申请人： William I. Lehrer
发明人： William I. Lehrer
IPC分类号： H01L23/29 , H01L23/31
CPC分类号： H01L23/3192 , H01L23/291 , H01L2924/0002
摘要： A thick glass passivation layer comprises an alternating sequence of structurally dissimilar but chemically compatible layers of material over the surface of a substrate, so as to provide sufficient elasticity to compensate for thermal expansion differences that would otherwise crack causing in thick monolithic films. A first layer comprises glass that has been deposited over the surface of the structure using chemical vapor deposition. A second layer of the passivating glass material is then provided on the substrate using a spinning technique. The chemical vapor deposition and spun layers continue to be applied in an alternating fashion until a film having the desired thickness is formed. Each chemical vapor deposition layer provides an elastic cushion for the subsequently spun layers. The spun layers allows a planar topography to be maintained without the need for high temperatures.
摘要翻译：厚玻璃钝化层包括在衬底的表面上的结构上不相似但化学相容的材料层的交替序列，以便提供足够的弹性以补偿否则在厚的整体膜中会导致的热膨胀差异。第一层包括使用化学气相沉积沉积在结构表面上的玻璃。然后使用旋转技术在基板上提供第二层钝化玻璃材料。化学气相沉积和纺丝层继续以交替的方式施加，直到形成具有所需厚度的膜。每个化学气相沉积层为随后的纺丝层提供弹性垫。纺丝层允许在不需要高温的情况下维持平面形貌。

2. 发明授权

US4629912A Schottky shunt integrated injection 失效
标题翻译：肖特基分路整合注射
公开(公告)号：US4629912A
公开(公告)日：1986-12-16
申请号：US776992
申请日：1985-09-16
申请人： James M. Early
发明人： James M. Early
IPC分类号： H01L27/02 , H01L27/07 , H03K19/091 , H01L29/04 , H03K19/003 , H03K19/013
CPC分类号： H01L27/0233 , H01L27/0766
摘要： An improved integrated injection logic structure utilizes a current mirror in conjunction with each switching transistor (M.sub.1, M.sub.2) of the integrated injection logic circuit of this invention by connecting one of a plurality of collectors (O.sub.0, P.sub.0) of the switching transistor to the base of said switching transistor. In this manner, the current flowing through conducting switching transistors is limited by the current mirror. This limited current flow through conducting switching transistors, as well as the use of voltage pull up means (D.sub.1, D.sub.2) connected to the collectors of the switching transistors prevents the saturation of conducting switching transistors. This results in an increase in the voltage on the collectors of conducting switching transistors and a decrease in the voltage swing between a logical one and a logical zero, thereby substantially increasing the speed of the integrated injection logic circuit of this invention as compared to prior art integrated injection logic circuits. The voltage pull up means connected to the collectors of the switching transistors may comprise resistors or preferably forward biased Schottky diodes connected between a voltage source (V.sub.dd) and the collectors of the switching transistors. This invention is also suitable for use in MOS circuits.
摘要翻译：改进的集成注入逻辑结构通过将开关晶体管的多个集电极（O0，P0）中的一个连接到基极来利用本发明的集成注入逻辑电路的每个开关晶体管（M1，M2）结合电流镜的所述开关晶体管。以这种方式，流经导通开关晶体管的电流受到电流镜的限制。通过导通开关晶体管的这种有限的电流以及连接到开关晶体管的集电极的电压上拉装置（D1，D2）的使用防止了导通开关晶体管的饱和。这导致导通开关晶体管的集电极上的电压的增加和逻辑1和逻辑零之间的电压摆动的降低，从而与现有技术相比，本发明的集成注入逻辑电路的速度显着增加集成注入逻辑电路。连接到开关晶体管的集电极的电压上拉装置可以包括连接在电压源（Vdd）和开关晶体管的集电极之间的电阻器或优选的正向偏置肖特基二极管。本发明也适用于MOS电路。

3. 发明授权

US4465995A Method and apparatus for analyzing an analog-to-digital converter with a nonideal digital-to-analog converter 失效
标题翻译：用于使用非理想数模转换器分析模数转换器的方法和装置
公开(公告)号：US4465995A
公开(公告)日：1984-08-14
申请号：US364374
申请日：1982-04-01
申请人： Edwin A. Sloane
发明人： Edwin A. Sloane
IPC分类号： G01R31/28 , G06G7/19 , H03M1/00 , H03K13/00
CPC分类号： G06G7/19 , G01R31/28 , H03M1/1071
摘要： A method for statistically calibrating an analog-to-digital converter with an electronic test system. A digital-to-analog converter which has been calibrated by premeasured weighting coefficients with respect to two-state orthogonal signals is excited with two state signals at each input bit which together represent a single signal with uniform amplitude probability with respect to time, and wherein each excitation signal is orthogonal with respect to all other excitation signals. The output of the digital-to-analog converter is detected by the analog-to-digital converter under test. The digital time domain output signals are then mapped into a transform domain to obtain weighting coefficients of each bit of the output response. Finally the transform domain weighting coefficients are weighted by the reciprocal of the premeasured weighting coefficients to obtain the unbiased weight of each bit of the analog-to-digital converter under test. A preferred set of excitation signals is a set of Walsh function signals representing the digital equivalent of a linear ramp function.
摘要翻译：一种用电子测试系统对模数转换器进行统计校准的方法。已经通过相对于两状态正交信号的预先测量的加权系数校准的数模转换器在每个输入位处被两个状态信号激励，这两个状态信号一起表示相对于时间具有均匀振幅概率的单个信号，并且其中每个激励信号相对于所有其它激励信号是正交的。数模转换器的输出由被测数字转换器检测。然后将数字时域输出信号映射到变换域中，以获得输出响应的每个位的加权系数。最后，通过预先测量的加权系数的倒数对变换域加权系数进行加权，以获得待测模拟数字转换器的每个位的无偏置权重。优选的一组激励信号是表示线性斜坡函数的数字等价物的沃尔什函数信号的集合。

4. 发明授权

US4443493A Laser induced flow glass materials 失效
标题翻译：激光诱导流动玻璃材料
公开(公告)号：US4443493A
公开(公告)日：1984-04-17
申请号：US339600
申请日：1982-01-15
申请人： Michelangelo Delfino
发明人： Michelangelo Delfino
IPC分类号： H01L29/78 , H01L21/268 , H01L21/3105 , H01L21/316 , B05D3/06
CPC分类号： H01L21/268 , H01L21/3105
摘要： In a semiconductor device, laser energy is used to selectively heat various SiO.sub.2 based materials to elevated temperatures while maintaining the active device region and electrical interconnects at relatively low temperatures, to for example, induce densification and/or flow of the SiO.sub.2 based material to round off sharp edges and stops, without damaging or affecting the active region and electrical interconnects.
摘要翻译：在半导体器件中，激光能量用于将各种基于SiO 2的材料选择性地加热到升高的温度，同时保持活性器件区域和电互连在相对较低的温度下，例如引起SiO 2基材料的致密化和/或流动到圆形锐利的边缘和停止，而不损坏或影响有源区域和电气互连。

5. 发明授权

US4442449A Binary germanium-silicon interconnect and electrode structure for integrated circuits 失效
标题翻译：用于集成电路的二元锗硅互连和电极结构
公开(公告)号：US4442449A
公开(公告)日：1984-04-10
申请号：US243986
申请日：1981-03-16
申请人： William I. Lehrer , Bruce E. Deal
发明人： William I. Lehrer , Bruce E. Deal
IPC分类号： H01L29/78 , H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/532 , H01L29/43 , H01L29/163 , H01L29/54
CPC分类号： H01L23/53271 , H01L21/76886 , H01L2924/0002 , Y10S428/929 , Y10T428/12528 , Y10T428/12674
摘要： An interconnect structure for use in integrated circuits comprises a germanium-silicon binary alloy. Such an alloy is deposited on the semiconductor wafer from the co-deposition of germanium and silicon using chemical vapor deposition techniques of a type commonly used in the semiconductor industry. The resulting alloy can be oxidized, selectively removed and doped with selected impurities to provide a conductive lead pattern of a desired shape on the surface of a wafer.
摘要翻译：用于集成电路的互连结构包括锗 - 硅二元合金。使用在半导体工业中通常使用的类型的化学气相沉积技术，这种合金由锗和硅的共沉积沉积在半导体晶片上。所得合金可以被氧化，选择性地除去并掺杂选定的杂质，以在晶片的表面上提供所需形状的导电引线图形。

6. 发明授权

US4231110A Memory array with sequential row and column addressing 失效
标题翻译：具有顺序行和列寻址的存储器阵列
公开(公告)号：US4231110A
公开(公告)日：1980-10-28
申请号：US007103
申请日：1979-01-29
申请人： Jonathan J. Stinehelfer
发明人： Jonathan J. Stinehelfer
IPC分类号： G11C11/41 , G11C11/414 , G11C8/00 , G11C7/00
CPC分类号： G11C11/414
摘要： An electronic memory comprises a plurality of memory cells arranged in an array of rows and column, row address circuitry, column address circuitry, circuitry for sensing the logic states of the cells, and circuitry for delaying addressing of a selected column until after an addressed row has achieved a voltage level suitable for the sensing circuitry to sense. By so delaying the addressing of the selected column, the time required to read information out is reduced substantially--typically by a factor of two for a 1K or 2K.times.8-bit static memory.
摘要翻译：电子存储器包括以行和列阵列排列的多个存储器单元，行地址电路，列地址电路，用于感测单元的逻辑状态的电路，以及延迟所选列的寻址直到寻址行之后的电路已经实现了适合感测电路感测的电压电平。通过这样延迟对所选列的寻址，读出信息所需的时间被大大降低 - 对于1K或2K×8位静态存储器，通常为2倍。

7. 发明授权

US2998343A Process for making a hydraulic diaphragm 失效
标题翻译：制造液压隔膜的工艺
公开(公告)号：US2998343A
公开(公告)日：1961-08-29
申请号：US70666858
申请日：1958-01-02
申请人： GEN MOTORS CORP
发明人： JOHN GOLD , WILKINSON CHESTER J
IPC分类号： B29D99/00
CPC分类号： B29D99/005 , B29L2031/755 , Y10T156/1002 , Y10T428/31743 , Y10T428/31924 , Y10T442/674

8. 发明授权

US2850105A Propeller mechanism with means to vary the pitch change rate 失效
标题翻译：螺旋桨机构，具有改变音高变化率的手段
公开(公告)号：US2850105A
公开(公告)日：1958-09-02
申请号：US36437453
申请日：1953-06-26
申请人： GEN MOTORS CORP
发明人： BRANDES ROY H
IPC分类号： B64C11/40
CPC分类号： B64C11/40 , Y10T137/1171

9. 发明授权

US4386420A Dynamic read reference voltage generator 失效
标题翻译：动态读取参考电压发生器
公开(公告)号：US4386420A
公开(公告)日：1983-05-31
申请号：US313001
申请日：1981-10-19
申请人： Warren R. Ong
发明人： Warren R. Ong
IPC分类号： G11C7/14 , G11C11/416 , G11C7/00
CPC分类号： G11C11/416 , G11C7/14
摘要： A method and circuitry (5) for enhancing the reproducibility and reliability of circuitry for reading a memory array (10a, 10b, 10a', 10b') provides a dynamically generated reference voltage for the sensing circuitry. The invention senses the highest word line voltage and communicates a voltage derived therefrom to the sensing circuitry (26, 27, 28, 29; 26', 27', 28', 29'; 32, 33) to provide a reference voltage. A voltage clamp (62) is coupled to the circuitry for communicating the highest word line voltage (50) to prevent the reference voltge from following the word line too low during transitions. The invention is rendered compatible with the existing write circuitry associated with the memory array (10a, 10b, 10a', 10b') by the provision of disabling circuitry (65) coupled to the communicating circuitry (55, 57) and to the clamp (62). The disabling circuitry (65) is responsive to a write control signal and operates to prevent the high word line voltage from being communicated to the sensing circuitry, and further operates to allow the communication of lower voltage than would normally be permitted by the clamp (62).
摘要翻译：用于增强用于读取存储器阵列（10a，10b，10a'，10b'）的电路的再现性和可靠性的方法和电路（5）为感测电路提供动态产生的参考电压。本发明感测到最高的字线电压，并将从其导出的电压传送到感测电路（26,27,28,29; 26'，27'，28'，29'; 32,33）以提供参考电压。电压钳位器（62）耦合到用于传送最高字线电压（50）的电路，以防止在转换期间参考电压跟随字线太低。本发明通过提供耦合到通信电路（55,57）和钳位电路（55,57）的禁用电路（65）与现有的与存储器阵列（10a，10b，10a'，10b'）相关联的写入电路 62）。禁用电路（65）响应于写入控制信号并且操作以防止高字线电压被传送到感测电路，并且还进一步操作以允许比通常由钳位（62）允许的更低的电压通信）。

10. 发明授权

US4334157A Data latch with enable signal gating 失效
标题翻译：数据锁存与使能信号门控
公开(公告)号：US4334157A
公开(公告)日：1982-06-08
申请号：US123717
申请日：1980-02-22
申请人： David A. Ferris
发明人： David A. Ferris
IPC分类号： G11C11/411 , H03K3/288 , H03K17/00
CPC分类号： G11C11/411
摘要： A data latch of the kind having at least two operative modes, a transmitting or transparent mode or condition for transmitting data signals through the latch, and a latching mode or condition for latching and temporary storage by feedback of data signals in the latch. According to the invention there is provided in the data latch a pregate for pregating feedback signals in the latch. The pregate is adapted and coupled to provide positive feedback data signals for reinforcing previously entered data in the latching mode, and gating signals for passing input data in the transmitting mode.
摘要翻译：具有至少两种操作模式的数据锁存器，用于通过锁存器发送数据信号的发送或透明模式或条件，以及用于通过锁存器中的数据信号的反馈来锁存和临时存储的锁存模式或条件。根据本发明，在数据锁存器中提供了用于在锁存器中预示反馈信号的预分闸。前门被适配和耦合以提供用于在锁存模式下加强先前输入的数据的正反馈数据信号，以及用于在发送模式下传递输入数据的选通信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式