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1. 发明授权

US5583821A Storage cell using low powered/low threshold CMOS pass transistors having reduced charge leakage 失效
公开(公告)号：US5583821A
公开(公告)日：1996-12-10
申请号：US509599
申请日：1995-07-31
申请人： James W. Rose , Godfrey P. D'Souza , Jonathan J. Stinehelfer , James F. Testa
发明人： James W. Rose , Godfrey P. D'Souza , Jonathan J. Stinehelfer , James F. Testa
IPC分类号： G11C11/412 , G11C11/404 , G11C11/407 , G11C11/418 , G11C7/00
CPC分类号： G11C11/404 , G11C11/418
摘要： A storage cell includes a first bit line, a storage circuit, and a pass transistor. The storage circuit has a first storage node for holding a logic state indicative of a logic value. The pass transistor is coupled to the first bit line and the first storage node for establishing a conduction path therebetween. The pass transistor receives a bias voltage to switch the pass transistor into a substantially nonconducting state when the storage cell is not being accessed. The reverse bias on the first transistor substantially reduces the leakage current through the pass transistor.

2. 发明授权

US4488263A Bypass circuit for word line cell discharge current 失效
标题翻译：用于字线电池放电电流的旁路电路
公开(公告)号：US4488263A
公开(公告)日：1984-12-11
申请号：US363198
申请日：1982-03-29
申请人： William H. Herndon , Jonathan J. Stinehelfer
发明人： William H. Herndon , Jonathan J. Stinehelfer
IPC分类号： G11C11/414 , G11C11/415 , G11C11/40
CPC分类号： G11C11/415
摘要： A current bypass for a microelectric memory, such as a static RAM, diverts word line discharge current such that the current does not flow through the memory cells of a selected word line or along an upper word line conductor. In a first embodiment, the bypass comprises a resistor R1 (R2) and a diode D10 (D20) in series and coupled between an upper word line conductor 50 and word line discharge current source V.sub.CC, and a lower word line conductor 51 and word line discharge current sink 42. In another embodiment of the invention, a transistor Q10 (Q20) is used in lieu of the diode. By bypassing current from the upper word line conductor and word line memory cells, metal migration is eliminated and narrower metal lines may be used to form the word lines. By eliminating a flow of steady state discharge current through the memory cells, memory cell current saturation is eliminated.
摘要翻译：用于诸如静态RAM的微电存储器的电流旁路转移字线放电电流，使得电流不流过选定字线或沿着上字线导体的存储器单元。在第一实施例中，旁路包括串联的电阻器R1（R2）和二极管D10（D20），并耦合在上字线导体50和字线放电电流源VCC之间，并且下字线导体51和字线放电电流阱42.在本发明的另一个实施例中，使用晶体管Q10（Q20）代替二极管。通过绕过上部字线导体和字线存储器单元的电流，消除了金属迁移，并且可以使用较窄的金属线来形成字线。通过消除通过存储单元的稳态放电电流的流动，消除了存储单元电流饱和。

3. 发明授权

US4409675A Address gate for memories to protect stored data, and to simplify memory testing, and method of use thereof 失效
标题翻译：用于保存存储数据的存储器的地址门，以及简化存储器测试及其使用方法
公开(公告)号：US4409675A
公开(公告)日：1983-10-11
申请号：US219294
申请日：1980-12-22
申请人： Jonathan J. Stinehelfer
发明人： Jonathan J. Stinehelfer
IPC分类号： G11C11/413 , G06F7/78 , G06F12/06 , G11C8/00 , G11C29/10 , G11C7/00 , G11C29/00
CPC分类号： G06F7/785 , G11C8/00
摘要： An address gate for a random access memory includes a pair of emitter-coupled and collector-coupled transistors, and another transistor emitter-coupled to the pair of transistors. Complimentary outputs are read at the coupled emitters of the pair of transistors and the collector of the other transistor respectively, there being an input signal applied to the base of one of the pair of transistors, and a control signal applied to the base of the other of the pair of transistors, which overrides the operation of one of the pair of transistors when the control signal is in its high state.
摘要翻译：用于随机存取存储器的地址门包括一对发射极耦合和集电极耦合晶体管，以及发射极耦合到该对晶体管的另一晶体管。在一对晶体管的耦合发射极和另一个晶体管的集电极分别读取免费输出，施加到一对晶体管之一的基极的输入信号，以及施加到另一晶体管的基极的控制信号的一对晶体管，当控制信号处于高电平状态时，它们覆盖一对晶体管之一的工作。

4. 发明授权

US5471421A Storage cell using low powered/low threshold CMOS pass transistors having reduced charge leakage 失效
标题翻译：使用具有减少的电荷泄漏的低功率/低阈值CMOS传输晶体管的存储单元
公开(公告)号：US5471421A
公开(公告)日：1995-11-28
申请号：US358202
申请日：1994-12-16
申请人： James W. Rose , Godfrey P. D'Souza , Jonathan J. Stinehelfer , James F. Testa
发明人： James W. Rose , Godfrey P. D'Souza , Jonathan J. Stinehelfer , James F. Testa
IPC分类号： G11C11/412 , G11C11/404 , G11C11/407 , G11C11/418 , G11C13/00
CPC分类号： G11C11/404 , G11C11/418
摘要： A storage cell includes a first bit line, a storage circuit, and a pass transistor. The storage circuit has a first storage node for holding a logic state indicative of a logic value. The pass transistor is coupled to the first bit line and the first storage node for establishing a conduction path therebetween. The pass transistor receives a bias voltage to switch the pass transistor into a substantially nonconducting state when the storage cell is not being accessed. The reverse bias on the first transistor substantially reduces the leakage current through the pass transistor.
摘要翻译：存储单元包括第一位线，存储电路和传输晶体管。存储电路具有用于保持指示逻辑值的逻辑状态的第一存储节点。传输晶体管耦合到第一位线和第一存储节点，用于在它们之间建立传导路径。当存储单元不被访问时，传输晶体管接收偏置电压以将传输晶体管切换到基本上非导通状态。第一晶体管上的反向偏压基本上减小了通过晶体管的漏电流。

5. 发明授权

US4231110A Memory array with sequential row and column addressing 失效
标题翻译：具有顺序行和列寻址的存储器阵列
公开(公告)号：US4231110A
公开(公告)日：1980-10-28
申请号：US007103
申请日：1979-01-29
申请人： Jonathan J. Stinehelfer
发明人： Jonathan J. Stinehelfer
IPC分类号： G11C11/41 , G11C11/414 , G11C8/00 , G11C7/00
CPC分类号： G11C11/414
摘要： An electronic memory comprises a plurality of memory cells arranged in an array of rows and column, row address circuitry, column address circuitry, circuitry for sensing the logic states of the cells, and circuitry for delaying addressing of a selected column until after an addressed row has achieved a voltage level suitable for the sensing circuitry to sense. By so delaying the addressing of the selected column, the time required to read information out is reduced substantially--typically by a factor of two for a 1K or 2K.times.8-bit static memory.
摘要翻译：电子存储器包括以行和列阵列排列的多个存储器单元，行地址电路，列地址电路，用于感测单元的逻辑状态的电路，以及延迟所选列的寻址直到寻址行之后的电路已经实现了适合感测电路感测的电压电平。通过这样延迟对所选列的寻址，读出信息所需的时间被大大降低 - 对于1K或2K×8位静态存储器，通常为2倍。

6. 发明授权

US4168490A Addressable word line pull-down circuit 失效
标题翻译：可寻址字线下拉电路
公开(公告)号：US4168490A
公开(公告)日：1979-09-18
申请号：US918868
申请日：1978-06-26
申请人： Jonathan J. Stinehelfer
发明人： Jonathan J. Stinehelfer
IPC分类号： G11C11/415 , G11C7/02 , H03K5/20 , H04Q9/00
CPC分类号： G11C11/415
摘要： Computer circuitry for rapidly discharging the deselected word lines in high-speed very low power random access memories that may be accidentally triggered by noise pulses if permitted to decay at the normal rate.
摘要翻译：计算机电路，用于在高速非常低功率的随机存取存储器中快速放电取消选择的字线，如果允许以正常速率衰减，可能会被噪声脉冲意外地触发。

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